A Statistical Model to Predict the Performance Variation of Polysilicon TFTs Formed by Grain-Enhancement Technology

Cheng, C.F.; Singh, Joginder; Poon, M.C.; Kok, Chi-Wah; Chan, Mansun

doi:10.1109/ted.2004.838325

Cited by 19 publications

(7 citation statements)

References 16 publications

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“…Then, given a total area constraint for the solar cell module, we divide this area into 0.2µm 2 sized unit cells. The probability of having a GB within a unit cell is calculated using the formalism in [4].…”

Section: Unified Spice Modelmentioning

confidence: 99%

Modeling, design and cross-layer optimization of polysilicon solar cell based micro-scale energy harvesting systems

Mungan

Lü

Raghunathan

et al. 2012

Proceedings of the 2012 ACM/IEEE International Symposium on Low Power Electronics and Design

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This paper presents modeling, design and cross-layer optimization of polysilicon solar cell based micro-scale energy harvesting systems. The proposed design methodology is suitable for energy harvesting systems employed in low-cost applications, such as wireless sensor networks. Our approach is unique in achieving maximum output power by cross-layer optimization of poly-silicon solar cells (thickness, grain boundaries and cell configuration) and power converter circuits. Simulation results indicate that optimizing the solar cell along with the power converter improves the system output power by 16% compared to a baseline approach of optimizing the two components separately.

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Section: Unified Spice Modelmentioning

confidence: 99%

Modeling, design and cross-layer optimization of polysilicon solar cell based micro-scale energy harvesting systems

Mungan

Lü

Raghunathan

et al. 2012

Proceedings of the 2012 ACM/IEEE International Symposium on Low Power Electronics and Design

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“…In QMS, the grain-size distribution follows the Maxwell distribution [Cheng et al 2004] along the X and Y directions. Once the circuit layout is In both I on cases, is normalized to its value when GB is in the middle of the channel.…”

Section: Inherent Gb-induced Variationmentioning

confidence: 99%

An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs

Bansal²,

Ghosh

et al. 2008

J. Emerg. Technol. Comput. Syst.

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This article presents a holistic hybrid design methodology for low-power, low-cost, testable digital designs using low-temperature polycrystalline-silicon thin-film transistors (LTPS TFTs). An alternate scaling rule under low thermal budget (due to flexible substrate) is developed to improve the performance of TFTs in the presence of process variation. We demonstrate that LTPS TFTs can be further optimized for ultralow-power subthreshold operation with performances comparable to contemporary single-crystal silicon-on-insulator (c-Si SOI) devices after process optimization. The optimized LTPS TFTs with high current drivability and less variability can comprise a promising low-cost option to augment Si CMOS technology, opening up a plethora of new hybrid 3D applications. We illustrate one such application: IC testing. Testing of complex VLSI systems is a prime concern due to design cost of DFT circuits, area/delay overheads, and poor test confidence. To harness the benefits of TFT technology, a novel low-power, process-tolerant, generic, and reconfigurable test structure designed using LTPS TFTs is proposed to reduce the test cost, as well as to improve diagnosability and verifiability, of complex VLSI systems. Due to proper optimization of TFT devices, the proposed test structure consumes low power but operates with reasonable performance. Furthermore, the test circuits do not consume any silicon area because they can be integrated on-chip using 3D technology. Since the test architecture is reconfigurable, this This research was supported by DARPA. 13:2• J. Li et al.eliminates the need to redesign built-in-self-test (BIST) components that may vary from one processor generation to another. We have developed test structures using 200nm TFT devices and evaluated them on designs implemented in 130nm bulk CMOS. For circuit simulations, we have developed a SPICE-compatible model for TFT devices. The BIST components designed using the test structures operate at 0.8-4.3 GHz (compared to 8.2 GHz in bulk CMOS) with low power consumption. The enhanced scan cells partially implemented in TFT (3D hybrid design) consume ∼24% less power and ∼15-20% less area of Si die compared to conventional bulk-Si design (2D planar design), with minimal delay overhead.

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“…9. In QMS, the grain size distribution follows the Maxwell distribution [11] along X and Y directions. The key distribution parameter is the average grain size.…”

Section: Process Variation Estimation and Compensationmentioning

confidence: 99%

A generic and reconfigurable test paradigm using Low-cost integrated Poly-Si TFTs

Ghosh

Roy

2007

2007 IEEE International Test Conference

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A Statistical Model to Predict the Performance Variation of Polysilicon TFTs Formed by Grain-Enhancement Technology

Cited by 19 publications

References 16 publications

Modeling, design and cross-layer optimization of polysilicon solar cell based micro-scale energy harvesting systems

Modeling, design and cross-layer optimization of polysilicon solar cell based micro-scale energy harvesting systems

An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs

A generic and reconfigurable test paradigm using Low-cost integrated Poly-Si TFTs

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