A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks

Bhanja, Sanjukta; Lingasubramanian, Karthikeyan; Ranganathan, N.

doi:10.1145/1142980.1142990

Cited by 4 publications

(3 citation statements)

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“…In a minimal representation of a DAG, removing just one edge will collapse the entire dependency structure of the graph. For detailed explanations and proofs for the above postulates please read [10].…”

Section: A Backgroundmentioning

confidence: 99%

Probabilistic error modeling for sequential logic

Lingasubramanian

Bhanja

2007

2007 7th IEEE Conference on Nanotechnology (IEEE NANO)

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Reliability is a crucial issue in nanoscale devices including both CMOS (beyond 22nm) and non-CMOS. Devices in this regime tend to be more prone to errors due to thermal effects creating uncertainty in device characteristics. The transient nature of these errors commands the need for a probabilistic model that can represent the inherent circuit logic and can measure the errors. In sequential logic the error occurred in a particular time frame will be propagated to consecutive time frames thereby making the device more volatile. Any model that can represent a sequential logic should handle both spatial dependencies between nodes in a single time slice and temporal dependencies between nodes of different time slices. While modeling error in sequential logic the complexity arises in handling the temporal dependencies due to the feedback. Essentially, the feedback makes the system non-causal where outputs depend not only on inputs but also its own previous values. Depending on the circuit structure and the nature of feedback, various circuits would offer different degree of temporal dependence. In this work we propose a probabilistic error model for sequential logic that can measure the average output error probability that account for the spatio-temporal nature of the inherent dependencies using an temporally evolving causal Bayesian Networks also called Dynamic Bayesian Networks.

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Section: A Backgroundmentioning

confidence: 99%

Probabilistic error modeling for sequential logic

Lingasubramanian

Bhanja

2007

2007 7th IEEE Conference on Nanotechnology (IEEE NANO)

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“…In Fig. 5(a), the block with the dotted square is the sensitization logic for 16 1 16 5 . This input signal value is set to logic one in order to model the effect of a 0-1-0 SEU occurring at node 16 at time frame 5.…”

Section: Tali: Timing-aware-logic-induced Soft Error Modelmentioning

confidence: 99%

“…This algorithm has been proven to converge to the correct probability estimates [17], without the added baggage of high space complexity and has been used in [16]. …”

Section: A Junction Tree Based Inferencementioning

confidence: 99%

A Timing-Aware Probabilistic Model for Single-Event-Upset Analysis

Rejimon

Bhanja

2006

IEEE Trans. VLSI Syst.

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Abstract-With device size shrinking and fast rising frequency ranges, effect of cosmic radiations and alpha particles known as Single-Event-Upset (SEU), Single-Event-transients (SET), is a growing concern in logic circuits. Accurate understanding and estimation of Single-Event-Upset sensitivities of individual nodes is necessary to achieve better soft error hardening techniques at logic level design abstraction. We propose a probabilistic framework to the study the effect of inputs, circuits structure and gate delays on Single-Event-Upset sensitivities of nodes in logic circuits as a single joint probability distribution function (pdf). To model the effect of timing, we consider signals at their possible arrival times as the random variables of interest. The underlying joint probability distribution function, consists of two components: ideal random variables without the effect of SEU and the random variables affected by the SEU. We use a Bayesian Network to represent the joint pdf which is a minimal compact directional graph for efficient probabilistic modeling of uncertainty. The attractive feature of this model is that not only does it use the conditional independence to arrive at a sparse structure, but also utilizes the same for smart probabilistic inference. We show that results with exact (exponential complexity) and approximate non-simulative stimulus-free inference (linear in number of nodes and samples) on benchmark circuits yield accurate estimates in reasonably small computation time.

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