A Stochastic Computational Approach for Accurate and Efficient Reliability Evaluation

Han, Jie; Chen, Hao; Liang, Jinghang; Zhu, Peican; Yang, Zhixi; Lombardi, Fabrizio

doi:10.1109/tc.2012.276

Cited by 117 publications

(73 citation statements)

References 39 publications

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“…Reliability is actually as important as other factors such as cost, performance, power consumption, area overhead and speed in the design of digital circuits [7], [8]. Reliability analysis of a logic circuit composed of logic gates, estimates the probability of a correct output value when the circuit is subject to an error stress such as incorrect input or internal gate failure.…”

Section: Introductionmentioning

confidence: 99%

Co-evolutionary Approach to Reduce Soft Error Rate of Implemented Circuits on SRAM_based FPGA

Jahanirad¹

2018

IJCA

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Soft errors such as Single Event Upset (SEU) have great effect on performance degradation of circuits implemented on SRAM_based FPGA. The soft error in configuration bits which control the logic and routing parts of the circuit, leads to permanent faults. In this paper, we have developed a coevolutionary method to reduce the effect of soft error on the implemented circuit on FPGA. This method is based on cooperation of genetic algorithm and ant colony optimization. The efficiency of co-evolutionary method has been proved by comparison of its results with the proposed genetic algorithm and ant colony optimization. The experimental results for some MCNC benchmark circuits show up to 34% improvement compare to genetic algorithm and up to 60% improvement against ant colony optimization.

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Section: Introductionmentioning

confidence: 99%

Co-evolutionary Approach to Reduce Soft Error Rate of Implemented Circuits on SRAM_based FPGA

Jahanirad¹

2018

IJCA

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“…Stochastic computation, first introduced in 1960s [1], has been widely used in many fields: neural network [2,3], digital image processing [4][5][6][7], channel decoding [8][9][10], MIMO detection [11,12], reliability evaluation [13], and so on. The main idea of stochastic computation is to represent continuous values with stochastic bit streams, which makes it possible to perform complex arithmetic computations with simple bitwise operations.…”

Section: Introductionmentioning

confidence: 99%

“…Han et al [13] use fixed-ones random-permutation sequences (FRSs) as input streams for stochastic circuits. They present the variance evaluation model for the basic stochastic computational elements, including AND gate and invert.…”

Section: Introductionmentioning

confidence: 99%

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Random Error Reduction Scheme for Combinational Stochastic Circuit

Ye¹,

Hu²

2017

Mathematical Problems in Engineering

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In conventional stochastic computation, all the input streams are Bernoulli sequences (BSs), which may result in large random error. To reduce random error and improve computational accuracy, some other sequences have been reported as alternatives to BSs. However, these sequences only apply to the specific stochastic circuits, have difficulties in hardware generation, or have length constraints. To this end, new sequences without these disadvantages should be considered. This paper proposes the random error analysis method for stochastic computation based on autocorrelation sequence (AS), which is more general than the conventional one based on BS. The analysis results show that we can use the proper ASs as input streams of stochastic circuits to reduce random error. On the basis of that conclusion, we propose the random error reduction scheme based on maximal concentrated autocorrelation sequence (MCAS) and BS, both of which are ASs. MCAS and BS are applicable to any combinational stochastic circuit, are easily generated by hardware, and have no length constraints, which avoid the disadvantages of sequences in the previous work. Moreover, we apply the proposed random error reduction scheme into several typical stochastic circuits as case studies. The simulation results confirm the effectiveness of the proposed scheme.

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“…The reason is manifold. First of all, the higher integration density and lower voltage/current thresholds have increased the likelihood of soft errors [2,3]. Secondly, process variations due to random dopant fluctuation or manufacturing defects have negative impacts on circuit performance and may cause circuits to malfunction [1].…”

Section: Introductionmentioning

confidence: 99%

Gate-Level Circuit Reliability Analysis: A Survey

Xiao

Chen

2014

VLSI Design

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Circuit reliability has become a growing concern in today's nanoelectronics, which motivates strong research interest over the years in reliability analysis and reliability-oriented circuit design. While quite a few approaches for circuit reliability analysis have been reported, there is a lack of comparative studies on their pros and cons in terms of both accuracy and efficiency. This paper provides an overview of some typical methods for reliability analysis with focus on gate-level circuits, large or small, with or without reconvergent fanouts. It is intended to help the readers gain an insight into the reliability issues, and their complexity as well as optional solutions. Understanding the reliability analysis is also a first step towards advanced circuit designs for improved reliability in the future research.

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A Stochastic Computational Approach for Accurate and Efficient Reliability Evaluation

Cited by 117 publications

References 39 publications

Co-evolutionary Approach to Reduce Soft Error Rate of Implemented Circuits on SRAM_based FPGA

Co-evolutionary Approach to Reduce Soft Error Rate of Implemented Circuits on SRAM_based FPGA

Random Error Reduction Scheme for Combinational Stochastic Circuit

Gate-Level Circuit Reliability Analysis: A Survey

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