A Streaming High-Throughput Linear Sorter System with Contention Buffering

Ortiz, Jorge; Andrews, Davıd L.

doi:10.1155/2011/963539

Cited by 7 publications

(4 citation statements)

References 13 publications

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“…Systolic arrays have been well researched and many parallel algorithms are published as systolic arrays. In particular, the idea of using a linear array of sorting cells to implement insertion sort is well understood [55,9,45,5]. However, rather than being described as an unrolled loop, systolic arrays are often described as components communicating by streams of data.…”

Section: Explicit Systolic Array For Insertion Sortmentioning

confidence: 99%

Parallel Programming for FPGAs

Kastner¹,

Matai²,

Neuendorffer³

2018

Preprint

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Many people have contributed to making this book happen. Probably first and foremost are the many people who have done research in the area of High-Level Synthesis. Underlying each of the applications in this book are many individual synthesis and mapping technologies which combine to result in high-quality implementations.Many people have worked directly on the Vivado R HLS tool over the years. From the beginning in Jason Cong's research group at UCLA as the AutoPilot tool, to making a commercial product at AutoESL Inc., to widespread adoption at Xilinx, it's taken many hours of engineering to build an effective tool. To Zhiru Zhang, Yiping Fan, Bin Liu, Guoling Han, Kecheng Hao, Peichen Pan, Devadas Varma, Chuck Song, and many others: your efforts are greatly appreciated.The idea for this book originally arose out of a hallway conversation with Salil Raje shortly after Xilinx acquired the AutoESL technology. Much thanks to Salil for his early encouragement and financial support. Ivo Bolsens and Kees Vissers also had the trust that we could make something worth the effort. Thanks to you all for having the patience to wait for good things to emerge. This book would not have been possible without substantial support from the UCSD Wireless Embedded Systems Program. This book grew out of the need to make a hardware design class that could be broadly applicable to students coming from a mix of software and hardware backgrounds. The program provided substantial resources in terms of lab instructors, teaching assistants, and supplies that were invaluable as we developed (and re-developed) the curriculum that eventually morphed into this book. Thanks to all the UCSD 237C students over the years for providing feedback on what made sense, what didn't, and generally acting as guinea pigs over many revisions of the class and this book. Your suggestions and feedback were extremely helpful. A special thanks to the TAs for these classes, notable Alireza Khodamoradi, Pingfan Meng, Dajung Lee, Quentin Gautier, and Armaiti Ardeshiricham; they certainly felt the growing pains a lot more than the instructor.Various colleagues have been subjected to early drafts of the book, including Zhiru Zhang, Mike Wirthlin, Jonathan Corbett. We appreciate your feedback.

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Section: Explicit Systolic Array For Insertion Sortmentioning

confidence: 99%

Parallel Programming for FPGAs

Kastner¹,

Matai²,

Neuendorffer³

2018

Preprint

View full text Add to dashboard Cite

show abstract

“…Furthermore, specialized hardware such as priority schedulers may have diverse data processing and arrival times that must be taken into account if the system is to work in a pipelined fashion. Because pipelined systems can't move on to the next stage until the previous one is finished, pausing on a stage can possibly halt the pipeline's progress until data is available [29]. Other hardware sorting systems, such as Bitonic sorting networks [30,31], are effectively rendered obsolete by this characteristic, as they can only obtain high throughput when acting on all data sets that are readily available.…”

Section: Introductionmentioning

confidence: 99%

Designing an Efficient Hardware Accelerator for Data Sorting Integrated With a Risc-V

Preethi¹,

G²,

Augustine³

et al. 2022

INDJCSE

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In microprocessor architecture, amid a few blocks outcome of the optimized sorting algorithm has proved its impact on the results. Sorters can be implemented in domains that includes data centers, cloud computing servers for IoT applications. Sorters can be implemented on hardware, by deploying the developed sorter on Field Programmable Gate Array (FPGA). By contrasting factors like power consumption, implementation time, and implementation space with those of the proposed algorithm, it is possible to show the shortcomings of existing sorters like Bubble sort, Bitonic sort, and Odd-Even sort. This approves that the sorter with higher capability will perform better for sorting involving large numbers, this helps in designing of large-scale sorting for aforementioned applications. Few sorters were compared based on the parameters and it was concluded that comparison-free odd-even was having upper hand. Hence, the optimized sorter was implemented on the MicroBlaze, which is based on RISC-V architecture.

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“…extracting items with the desired characteristics). The majority of such problems can be solved in two of the most frequently investigated highly-parallel circuits based on sorting [2] and linear [3] networks. The majority of sorting networks implemented in hardware use Batcher even-odd and bitonic mergers [4].…”

mentioning

confidence: 99%

“…The majority of sorting networks implemented in hardware use Batcher even-odd and bitonic mergers [4]. There are limitations for both circuits [4] and [3] because they either introduce a very long propagation delay in [4] or are only suitable for a very small number of items in [3]. This conclusion is also valid for partially combinational and partially sequential networks described in [5].…”

mentioning

confidence: 99%

Fast Processing of Non-repeated Values in Hardware

Skliarova¹,

Sklyarov²,

Sudnitson³

2017

ElAEE

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The paper suggests a technique for fast data processing of unique and constrained items. The technique is based on two methods that involve: 1) address-based data sorting; and 2) communication-time networks. Input data are received one by one from a sequential channel. The first method enables undesirable values (e.g. previously taken or explicitly blocked) to be discarded. Although this method is chosen from the scope of data sorting, it is used in the paper (after some adjustments) for filtering. The second method enables each data item to be properly handled during communication time. For example, in case of data sorting it means that as soon as a new item is received it will immediately be placed in a proper position of the produced sorted subset that is composed of all previously acquired items. The circuits that implement the proposed methods have been entirely modeled and verified in software, then described in VHDL, synthesized and implemented in hardware, and finally evaluated. The results have shown that the proposed solutions are well suited for real-time applications. Index Terms-Address-based sorting; data filtering; sorting networks; communication-time circuits; FPGA. I. INTRODUCTIONData processing is one of the most common procedures in computational systems. Examples of such processing are data sorting/searching, discovering of frequent items, filtering and so on. Very often different operations over data are implemented in highly parallel networks that take input values and convert them to output values in a combinational circuit. The output values are not formed immediately because input signals pass through logic elements each of which causes a delay on a way of the signals from the inputs to the outputs. In many practical applications we would like to handle just non-repeated values, i.e. each of such values is unique. Let us consider, for instance, a set of natural values: {4, 0, 18, 5, 6, 4, 3, 3, 4} and some of them (e.g. the values 3 and 4) are repeated. Hence, the set of unique or nonrepeated values is {4, 0, 18, 5, 6, 3}. For many practical applications that can be found in cryptography, bioinformatics, feature extraction, data mining and some

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A Streaming High-Throughput Linear Sorter System with Contention Buffering

Cited by 7 publications

References 13 publications

Parallel Programming for FPGAs

Parallel Programming for FPGAs

Designing an Efficient Hardware Accelerator for Data Sorting Integrated With a Risc-V

Fast Processing of Non-repeated Values in Hardware

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