A Strength Pareto Evolutionary Algorithm for Optimizing System-On-Chip Test Schedules

Marrouche, Wissam; Farah, Rana; Harmanani, Haidar M.

doi:10.1142/s1469026818500104

Cited by 6 publications

(3 citation statements)

References 16 publications

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“…Sheshadri et al [40] proposed DVFS-based SoC test scheduling solutions for optimization through selecting clock frequency and supply voltages election. Shao et al [41] proposed the Process Algebra (PA) algorithm. To save time, Rohini and Salivahanan [42] proposed the Fuzzy and PA algorithms.…”

Section: Literature Reviewmentioning

confidence: 99%

Test Scheduling and Test Time Minimization of System-on-Chip Using Modified BAT Algorithm

et al. 2022

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System-on-Chip (SoC) is a structure in which semiconductor components are integrated into a single die. As a result, testing time should be reduced to achieve a low cost for each chip. Effective test scheduling can reduce the SoC testing time, which is more challenging due to its complexity. In this paper, the modified BAT algorithm-based test scheduling is proposed. Testing is carried out on the SoC ITC'02 benchmark circuits. The Modified Bat method is a recently heuristic algorithm that performs global optimization by imitating bat echolocation. Compared to other state-of-the-art algorithms, the Modified BAT Optimization method reduces testing time on SoCs. This paper improves the algorithm's exploration process by adjusting the equation for bat loudness (A0) and pulse emission rate (r). The modified BAT algorithm converges to the optimal solution faster. It has been used in 14 international standard test functions. The test results indicate that the modified BAT algorithm has a fast convergence speed, which minimizes the testing time compared to other evolutionary algorithms on the ITC'02 SoC benchmark circuits.

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Section: Literature Reviewmentioning

confidence: 99%

Test Scheduling and Test Time Minimization of System-on-Chip Using Modified BAT Algorithm

et al. 2022

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“…During the testing of interconnects, test stimuli are generated and the response is observed. All the cores need to be tested [4,5].…”

Section: Introductionmentioning

confidence: 99%

Test scheduling for system on chip using modified firefly and modified ABC algorithms

2019

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The system-on-chip (SoC) is an integration of millions of electronic components, there is always a chance for faults to occur due to manufacturing defects. In order to solve this problem, it is essential to test the manufactured chips. The time spent on testing increases the testing cost which reflects on the cost of the chip. While testing the SoC, core accessibility and testing time are the main issues to be considered. In order to reduce the testing time, test scheduling has to be performed in an effective manner. In this article ACO, Modified ACO, ABC, Modified ABC, Firefly and Modified Firefly test scheduling algorithms were tested on two SoC benchmark circuits. Experimental results show that the Modified ABC algorithm performs better than the other algorithms used in test scheduling. When compared with ACO, Modified ACO, ABC, Firefly and Modified Firefly algorithms, the Modified ABC algorithm's testing time has been reduced by 82%, 69%, 25%, 43% and 48% for d695 SoC and 80%, 73%, 20%, 41% and 47% for p22810 SoC benchmark circuits respectively.

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“…These components have an impact on the vector memory required on Automatic Test Equipment (ATE). The wrapper is a thin shell surrounding the core acting as an interface between the core and TAM [1][2][3].…”

Section: Introductionmentioning

confidence: 99%

Test Scheduling of Core Based System-on-Chip Using Modified Ant Colony Optimization

Chandrasekaran¹,

Vanchinathan²,

Chinraj³

2019

JESA

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A System-on-Chip (SoC) is an integrated circuit that combines various electronic components in a single die. The SoC components mostly involve user-defined logic, embedded memories, analog, digital and mixed-signal blocks. The testing of an SoC for manufacturing defects is an important task due to IC design complexity, further, it also affects the final cost of the chip. Due to the high complexity involved in SoC test scheduling, various techniques were suggested to reduce the testing time. This paper introduces a novel SoC test scheduling technique based on a Modified Ant Colony Optimization (MACO) algorithm. The testing is performed on the benchmark circuits of ITC'02. The experiments performed on d695 and p22810 SoC benchmark circuits. The results show that the MACO algorithm can achieve reduced test time compared to the ACO algorithm. When compared with ACO, the proposed algorithm MACO reduces the testing time by 47% and 10% for d695 and p22810 SoC benchmark circuits respectively.

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A Strength Pareto Evolutionary Algorithm for Optimizing System-On-Chip Test Schedules

Cited by 6 publications

References 16 publications

Test Scheduling and Test Time Minimization of System-on-Chip Using Modified BAT Algorithm

Test Scheduling and Test Time Minimization of System-on-Chip Using Modified BAT Algorithm

Test scheduling for system on chip using modified firefly and modified ABC algorithms

Test Scheduling of Core Based System-on-Chip Using Modified Ant Colony Optimization

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