A study of 90nm MOSFET subthreshold hump characteristics using newly developed MOSFET array test structure

Mizumura, A.; Ohishi, Tomoji; Yokoyama, N.; Nonaka, M.; Tanaka, Shigeru; Ammo, H.

doi:10.1109/icmts.2005.1452215

Cited by 8 publications

(1 citation statement)

References 10 publications

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“…To study such kind of phenomena, it is required many MOSFET Design of Experiment (DOE) so that MOSFET array structure [3]- [8] is one of useful design solutions to do that in limited area of chip. Mostly MOSFET array structure, however, has difficulty to measure accurate Ioff measurement, because array structure has many paths to contaminate Ioff of Device Under Test (OUT) with Ioff of other MOSFETs.…”

Section: Introductionmentioning

confidence: 99%

Advanced ioff measureable MOSFET array with eliminating leakage current of peripheral circuits

Suzuki¹,

Mori²,

Oishi³

et al. 2016

2016 International Conference on Microelectronic Test Structures (ICMTS)

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A Novel Ioff measurable MOSFET array has been developed. Body bias of peripheral circuit is controlled in order to eliminate the unwanted leakage current in peripheral circuit. SPICE simulation results indicate 1O-14 A or less of Ioff can be measured, and it is demonstrated that around 10-12 A of loff can be measured directly without any additional correction measurement. Since it can be fit into scribe line, Ion and loff can be measured with high accuracy for plenty of MOSFETs during mass production. In addition, MOSFET characteristics depending on various types of layout parameters will be able to extract efficiently.

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Section: Introductionmentioning

confidence: 99%