A study of fluorine implant in the formation of low leakage P&amp;#x002B;/N junction in BiCMOS technologies

Saad, Siti Zubaidah Md; Lik, Tan Chan; Othman, Marhanis Abu; Holger, Poehle; Herman, Sukreen Hana

doi:10.1109/escinano.2012.6149654

Cited by 3 publications

(1 citation statement)

References 6 publications

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“…The leakage current of the PN junction is caused by the drift of minority carriers at the edge of the depletion region and the recombination of electron-hole pairs in the depletion region. Generally, the leakage current of PN junction in 0.18 µm CMOS technology is in the order of aA/µm 2 , which is a low leakage current level in the CMOS circuit [24,25].…”

Section: Analysis Of Leakage Currentmentioning

confidence: 99%

The Design of a Low Noise and Low Power Current Readout Circuit for Sub-pA Current Detection Based on Charge Distribution Model

Jiang

Chen

et al. 2022

Electronics

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In this article, we proposed an analytical model based on charge distribution for switched-capacitor trans-impedance amplifiers (SCTIAs). The changes in the load state of the amplifier under different operating conditions and the influence of the gain of the operational amplifier (Opamp) on the trans-impedance gain are analyzed to improve the design theory of switched-capacitor trans-impedance amplifiers. According to the conclusion drawn from the analysis, the trans-impedance amplifier (TIA) has been designed by adopting “correlated double sampling technology” and “cross-connection technology” to optimize input-referred noise current, power consumption, and trans-impedance gain. As a result, the trans-impedance gain reaches up to 206 dB, while the bandwidth is 3 kHz. The current readout system achieves an input-referred noise current floor of 2.96 fA/Hz at 1 kHz, and the power consumption of the system is 0.643 mW. The circuit has been simulated with the technology of 0.18 μm, and the layout area is 1000 μm × 500 μm.

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Section: Analysis Of Leakage Currentmentioning

confidence: 99%

The Design of a Low Noise and Low Power Current Readout Circuit for Sub-pA Current Detection Based on Charge Distribution Model

Jiang

Chen

et al. 2022

Electronics

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A Strategy Of Eliminating Salicide Block Film Bubbles

Chen

Liu

Bao

2022

2022 China Semiconductor Technology International Conference (CSTIC)

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An improved P+/N diode leakage current in BiCMOS technologies with fluorine co-implant

Saad

Lik

Othman

et al. 2012

2012 10th IEEE International Conference on Semiconductor Electronics (ICSE)

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A study of fluorine implant in the formation of low leakage P+/N junction in BiCMOS technologies

Cited by 3 publications

References 6 publications

The Design of a Low Noise and Low Power Current Readout Circuit for Sub-pA Current Detection Based on Charge Distribution Model

The Design of a Low Noise and Low Power Current Readout Circuit for Sub-pA Current Detection Based on Charge Distribution Model

A Strategy Of Eliminating Salicide Block Film Bubbles

An improved P+/N diode leakage current in BiCMOS technologies with fluorine co-implant

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A study of fluorine implant in the formation of low leakage P&#x002B;/N junction in BiCMOS technologies

Cited by 3 publications

References 6 publications

The Design of a Low Noise and Low Power Current Readout Circuit for Sub-pA Current Detection Based on Charge Distribution Model

The Design of a Low Noise and Low Power Current Readout Circuit for Sub-pA Current Detection Based on Charge Distribution Model

A Strategy Of Eliminating Salicide Block Film Bubbles

An improved P&#x002B;/N diode leakage current in BiCMOS technologies with fluorine co-implant

Contact Info

Product

Resources

About

A study of fluorine implant in the formation of low leakage P+/N junction in BiCMOS technologies

An improved P+/N diode leakage current in BiCMOS technologies with fluorine co-implant