A study of latch-up mechanisms for adjacent pins on multiple power supply circuits

Abstract

Traditional latch-up (V DD -to-V SS ) in CMOS IC's is formed by the parasitic p-n-p-n structure between V DD and V SS . In modern technologies, although the guard rings and substrate/ well pickups could efficiently overcome the latch-up failure in CMOS ICs, the latch-up failure phenomenon is still existed in many special application circuits. With mixed signal design requirements, there are more than 2 kinds of devices that are deployed in one chip to implement the design with higher voltage system on the advanced technologies with lower voltage application in the mixed-voltage process. Therefore, these comprehensive process and design approaches could provide more flexibility for the chips to be connected with older system [1][2]. A latch-up phenomenon is reported here that the latch-up current path occurs between adjacent power pins of 65nm process, IO circuit is powered by different power supplies. In this product, IO circuitry is with 3.3V and core circuitry is with 1.2V power supply. Because there is no V DD -to-V DD latch-up rule, the 3.3V n-well to 1.2V n-well space was < 10 um (note: without any guard rings in between). Latch-up immunity of I/O pins resulted from a higher substrate potential required on the base-emitter junction forward bias of LQpnp. Conventional I/O Latch-Up: V DD -to-V SSLatch-Up is a major and inherent problem in CMOS caused by an internal positive feedback mechanism that gives rise to temporary or permanent loss of circuit function. In CMOS integrated circuits, traditional latchup is formed by the parasitic SCR (Silicon-Controlled-Rectifier) path between V DD and V SS . This parasitic path is inherent in the bulk CMOS ICs. When the SCR path is triggered on to conduct a huge current from V DD to V SS , the chip is often burned out. The equivalent circuit of the SCR path is shown in Fig. 1. (a); and the cross-sectional view of this path in a p-substrate bulk CMOS technology is illustrated in Fig. 1. (b). Necessary conditions for latch-up are that the emitter-base junction of both parasitic bipolar transistors must be forward biased. a) βn*βp > 1, b) V DD > V H , and c) There is a minimum latch-up trigger time for which the stimulus must be present in order for the circuit to be latched up. I-V characteristic of p-n-p-n is shown in Fig. 2. (a) (b) Fig.1. (a) The equivalent circuit, including well and substrate resistance, and (b) The cross-sectional view, of the traditional latch-up path in a p-substrate bulk CMOS technology.Fig.2 I-V characteristic of p-n-p-n P-SubN-Well P-Well P+ P+ N+ SCR Path VDD VSS VQ pnp LQ npn N+ N+ P+ Rwell RSub P-Sub N-Well P-Well P+ P+ N+ SCR Path VDD VSS VQ pnp LQ npn N+ N+ P+ Rwell RSub V H : holding voltage I H : holding current V trig : triggering voltage V H : holding voltage I H : holding current V trig : triggering voltage VSS VDD Rwell RSub LQ pnp VQ npn + + --V EB V BE VSS VDD Rwell RSub LQ pnp VQ npn + + --V EB V BE 78 978-1-4799-0480-8/13/$31.00 c 2013 IEEE