A Study of SCEs and Analog FOMs in GS-DG-MOSFET with Lateral Asymmetric Channel Doping

Sahu, Prasanna Kumar; Mohapatra, Sushanta Kumar; Pradhan, K P

doi:10.5573/jsts.2013.13.6.647

Cited by 7 publications

(3 citation statements)

References 25 publications

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“…9 Similarly, the impact of gate metal work function on various performances of GS-DG MOS-FET has been reported. 10 Sahu et al, 11 have demonstrated extensively about the effect of halo implanted doping profile, i.e., single halo (SH) and double halo (DH) in DG MOSFET. Finally in Pradhan et al, 12 a novel device design i.e., triple material (TM) gate metal with halo implanted doping profile (SH and DH) has been introduced and various dc performances have been closely analyzed.…”

mentioning

confidence: 99%

Impact of Channel and Metal Gate Work Function on GS-DG MOSFET: A Linearity Analysis

Pradhan¹,

Mohapatra²,

Sahu³

2015

ECS J. Solid State Sci. Technol.

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The current work reveals the substantial benefits of the various gate and channel engineering concepts, as well as the combination of both on the gate stack double gate (GS-DG) MOSFET. It is demonstrated that post implementation of tri material (TM) gate electrode and halo doping in the channel are significantly alleviated various performance metrics of GS-DG MOSFET. The study is based on surface potential, e-mobility, e-field, threshold voltage (Vth), subthreshold swing (SS), on-current (Ion), off-state current (Ioff), transconductance (gm1), second order voltage intercept point (VIP2), third order voltage intercept point (VIP3), third order intercept input power (IIP3), intermodulation distortion (IMD3), 1-db compression point, and higher order transconductance coefficients gm2, and gm3. Optimal device design parameters and trade-offs are examined through 2-D Sentaurus device simulator. The results are significant and reliable for RFICs with nanoscale MOSFETs.

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confidence: 99%

Impact of Channel and Metal Gate Work Function on GS-DG MOSFET: A Linearity Analysis

Pradhan¹,

Mohapatra²,

Sahu³

2015

ECS J. Solid State Sci. Technol.

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“…The multi-gate structures like Double Gate (DG) MOSFET fabricated on SOI wafers is one of the most promising candidates due to its attractive features of low leakage current, high current drivability (I on ), transconductance (g m ), reduced short channel effects (SCEs), steeper subthreshold slopes, and suppression of latch-up phenomenon [26]- [31]. In a recent work [32]- [34], a detailed analysis of inflection point to examine its reliability issues over a wide range of temperature variations (100 K-400 K) for both analog and RF applications of DG MOSFET with HKMG technology was reported.…”

Section: Significance Of Ztc Biasmentioning

confidence: 99%

ZTC bias point of advanced fin based device: The importance and exploration

2015

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The present understanding of this work is about to evaluate and resolve the temperature compensation point (TCP) or zero temperature coefficient (ZTC) point for a sub-20 nm FinFET. The sensitivity of geometry parameters on assorted performances of Fin based device and its reliability over ample range of temperatures i.e. 25 0 C to 225 0 C is reviewed to extend the benchmark of device scalability. The impact of fin height (H Fin), fin width (W Fin), and temperature (T) on immense performance metrics including on-off ratio (I on /I off), transconductance (g m), gain (A V), cutoff frequency (f T), static power dissipation (P D), energy (E), energy delay product (EDP), and sweet spot (g m f T /I D) of the FinFET is successfully carried out by commercially available TCAD simulator Sentaurus TM from Synopsis Inc.

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“…As channel length scaling of the conventional metaloxide-semiconductor field-effect transistors (MOSFETs) continues, they encounter several issues closely related with short-channel effects (SCEs) [1][2][3][4]. In the shortchannel MOSFETs, the presence of back-to-back two p-n junctions becomes more prominent as a weakness.…”

Section: Introductionmentioning

confidence: 99%

Design and Analysis of Sub-10 nm Junctionless Fin-Shaped Field-Effect Transistors

Kim¹,

Seo²,

Yoon³

et al. 2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-We design and analyze the n-channel junctionless fin-shaped field-effect transistor (JL FinFET) with 10-nm gate length and compare its performances with those of the conventional bulktype fin-shaped FET (conventional bulk FinFET). A three-dimensional (3-D) device simulations were performed to optimize the device design parameters including the width (W fin ) and height (H fin ) of the fin as well as the channel doping concentration (N ch ). Based on the design optimization, the two devices were compared in terms of direct-current (DC) and radio-frequency (RF) characteristics. The results reveal that the JL FinFET has better subthreshold swing, and more effectively suppresses short-channel effects (SCEs) than the conventional bulk FinFET.Index Terms-Junctionless, fin-shaped field-effect transistor (FinFET), short-channel effect (SCE), 3-D device simulation

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A Study of SCEs and Analog FOMs in GS-DG-MOSFET with Lateral Asymmetric Channel Doping

Cited by 7 publications

References 25 publications

Impact of Channel and Metal Gate Work Function on GS-DG MOSFET: A Linearity Analysis

Impact of Channel and Metal Gate Work Function on GS-DG MOSFET: A Linearity Analysis

ZTC bias point of advanced fin based device: The importance and exploration

Design and Analysis of Sub-10 nm Junctionless Fin-Shaped Field-Effect Transistors

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