A study of the threshold voltage variation for ultra-small bulk and SOI CMOS

Takeuchi, Kiyoshi; Koh, Risho; Mogami, Tohru

doi:10.1109/16.944188

Cited by 66 publications

(22 citation statements)

References 21 publications

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“…Among the various sources of device parameter variation, random dopant fluctuation is especially detrimental to SRAM yield, especially in RSNM. Sensitivity analyses of SRAM read and write metrics identify the PD and PG transistor threshold voltages as the most significant parameters for variation [11]. RSNM is especially sensitive to mismatch between the two PD transistors [11]- [13].…”

Section: Device Architecturesmentioning

confidence: 99%

SRAM Read/Write Margin Enhancements Using FinFETs

Carlson

Guo

Balasubramanian

et al. 2010

IEEE Trans. VLSI Syst.

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Abstract-Process-induced variations and sub-threshold leakage in bulk-Si technology limit the scaling of SRAM into sub-32 nm nodes. New device architectures are being considered to improve control and reduce short channel effects. Among the likely candidates, FinFETs are the most attractive option because of their good scalability and possibilities for further SRAM performance and yield enhancement through independent gating. The enhancements to read/write margins and yield are investigated in detail for two cell designs employing independently gated FinFETs. It is shown that FinFET-based 6-T SRAM cells designed with pass-gate feedback (PGFB) achieve significant improvements in the cell read stability without area penalty. The write-ability of the cell can be improved through the use of pull-up write gating (PUWG) with a separate write word line (WWL). The benefits of these two approaches are complementary and additive, allowing for simultaneous read and write yield enhancements when the PGFB and PUWG designs are used in combination.

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Section: Device Architecturesmentioning

confidence: 99%

SRAM Read/Write Margin Enhancements Using FinFETs

Carlson

Guo

Balasubramanian

et al. 2010

IEEE Trans. VLSI Syst.

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“…Previous work on random threshold voltage variations between neighboring, small geometry SRAM cell transistors due to dopant fluctuations [1][2][3][4], line edge roughness [5] and poly gate grain size variations [6] have been shown to limit the DC Read stability of SRAMs [7][8][9][10]. The impact of VT fluctuations on SRAM cell DC write margins is reported in this work, for the first time, and is shown to be the more limiting case.…”

Section: Introductionmentioning

confidence: 69%

Fluctuation limits & amp; scaling opportunities for CMOS SRAM cells

Bhavnagarwala

Kosonocky

Radens

et al.

IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.

141

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“…This decreasing scale allows in principle to include more transistors on a chip thereby enabling larger, faster, cheaper circuits to be built -widely captured through Moore's law [2]. However, it is now accepted that previous assumptions on the uniformity of transistor devices no longer hold true [3][4][5][6][7]. The atomic dimensions of transistor devices introduce variability caused by the microscopic (atomistic) differences of the transistors including for example the number and positioning of dopants in the silicon.…”

Section: Introductionmentioning

confidence: 99%

Secure, Performance-Oriented Data Management for nanoCMOS Electronics

Sinnott

Bayliss

Davenhall

et al. 2008

2008 IEEE Fourth International Conference on eScience

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The EPSRC pilot project Meeting the Design Challenges of nanoCMOS Electronics (nanoCMOS) is focused upon delivering a production level e-Infrastructure to meet the challenges facing the semiconductor industry in dealing with the next generation of 'atomic-scale' transistor devices. This scale means that previous assumptions on the uniformity of transistor devices in electronics circuit and systems design are no longer valid, and the industry as a whole must deal with variability throughout the design process. Infrastructures to tackle this problem must provide seamless access to very large HPC resources for computationally expensive simulation of statistic ensembles of microscopically varying physical devices, and manage the many hundreds of thousands of files and meta-data associated with these simulations. A key challenge in undertaking this is in protecting the intellectual property associated with the data, simulations and design process as a whole. In this paper we present the nanoCMOS infrastructure and outline an evaluation undertaken on the Storage Resource Broker (SRB) and the Andrew File System (AFS) considering in particular the extent that they meet the performance and security requirements of the nanoCMOS domain. We also describe how metadata management is supported and linked to simulations and results in a scalable and secure manner.

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A study of the threshold voltage variation for ultra-small bulk and SOI CMOS

Cited by 66 publications

References 21 publications

SRAM Read/Write Margin Enhancements Using FinFETs

SRAM Read/Write Margin Enhancements Using FinFETs

Fluctuation limits & amp; scaling opportunities for CMOS SRAM cells

Secure, Performance-Oriented Data Management for nanoCMOS Electronics

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