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The EPSRC pilot project Meeting the Design Challenges of nanoCMOS Electronics (nanoCMOS) is focused upon delivering a production level e-Infrastructure to meet the challenges facing the semiconductor industry in dealing with the next generation of 'atomic-scale' transistor devices. This scale means that previous assumptions on the uniformity of transistor devices in electronics circuit and systems design are no longer valid, and the industry as a whole must deal with variability throughout the design process. Infrastructures to tackle this problem must provide seamless access to very large HPC resources for computationally expensive simulation of statistic ensembles of microscopically varying physical devices, and manage the many hundreds of thousands of files and meta-data associated with these simulations. A key challenge in undertaking this is in protecting the intellectual property associated with the data, simulations and design process as a whole. In this paper we present the nanoCMOS infrastructure and outline an evaluation undertaken on the Storage Resource Broker (SRB) and the Andrew File System (AFS) considering in particular the extent that they meet the performance and security requirements of the nanoCMOS domain. We also describe how metadata management is supported and linked to simulations and results in a scalable and secure manner.

We describe the Circuit Reservation Software (CRS) developed by the ESLEA Project. Switchedcircuit networks can offer improved performance over conventional packet-switched networks for applications with some demanding types of network requirements. However, if switchedcircuit networks are used to connect scarce and expensive resources, such as supercomputers, then advanced reservations or bookings of circuits are necessary if the resources and networks are all to be used efficiently. We describe and discuss the CRS, a demonstrator system for making such advanced bookings.

The UK e-Science EPSRC pilot project Meeting the Design Challenges of nanoCMOS Electronics (nanoCMOS -www.nanocmos.ac.uk) was funded to address the challenges facing the global electronics semiconductor industry caused by the decreasing size of Complementary Metal Oxide Semiconductor (CMOS) transistors and the atomic variability present in devices manifest at these dimensions. Fundamental problems to be addressed include the modelling, understanding and predicting the effect of differences in the atomic structure of devices on their behaviour, and then using this information to guide electronic circuit and system designers who utilise CMOS components. In this paper we describe the e-Infrastructure that has been developed as part of the nanoCMOS project and outline how it supports large scale high performance computing (HPC) simulations of ensembles of devices which can subsequently be used to model and understand the impact that they have on very large electronic circuits. Key features of this e-Infrastructure include support for very large scale HPC utilization; dealing with federated data sets and associated metadata from multi-level simulations, and addressing challenges related to security and intellectual property protection of data, simulation codes and electronic designs as a whole.

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