A study of wafer and device charging during high current ion implantation

Basra, Vijay K.; McKenna, C.M.; Felch, S.B.

doi:10.1016/0168-583x(87)90857-3

Cited by 17 publications

(1 citation statement)

References 4 publications

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“…A square tunneling barrier (again presumably occurring from traps generated by the ion implantation) was also considered. The current voltage relationship for this situation is (42) J = e (-~• [6] The data from before is plotted in Fig. 18c and also gives a good straight line fit to the data.…”

Section: -[3]mentioning

confidence: 76%

Characterization of Enhanced Perimeter Leakage in MOS Structures Following Ion Implantation

Stinson

Osburn

1990

J. Electrochem. Soc.

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An enhanced leakage current through the gate oxide insulator following ion implantation of source/drain regions in self-aligned gate CMOS devices has been observed with thin gate oxides. A systematic characterization of this phenomena shows that the problem is related to physical damage around the edge of the structure, degrading the integrity of the insulator. Heavier implant atoms like arsenic result in more severely degraded gate structures while the effect of lighter atoms like boron is hardly apparent at normal dose levels. The mechanism for current flow through the structure remains tunneling (as it is normally for current flow through a MOS structure), and is modeled by a reduced tunneling barrier height.MOSFET devices having lithographic features of 0.5 ~m and under require very thin gate oxides and employ ion implantation into patterned gate electrodes to form selfaligned junctions. A low-field breakdown phenomena, through these thin gate oxides, associated with the arsenic source/drain implantation step (1 x 1015-1 x 10 I~ cm -2) for fabricating self-aligned MOSFETs was first reported in 1982 (1). For a 1 x 1016 As/cm 2 dose, at 50 keV, the group found an average breakdown field of 2.2 MV/cm for a 10 nm oxide thickness, whereas unimplanted control samples demonstrated breakdown fields well in excess of 10 MV/cm. The effect was seen in structures which had gate electrode edges directly over thin oxide regions, as is typical for source/drain implants in MOS transistor fabrication as shown in Fig. 1. Capacitor structures with their gate edges overlapping thicker field oxide did not demonstrate low-field breakdown. It was reported that the degradation of MOS dielectric breakdown was most severe in the thinnest gate oxides examined for the highest dose implants. This edge breakdown effect was subsequently described in several other publications (2-6). Flowers had found a similar effect for several other common doping methods besides ion implantation (2). He found that degradation occurred in MOS structures following POCla polysilicon doping, spin on doping techniques, as well as ion implantation. Phosphorus implantation was also demonstrated to degrade the oxide dielectric strength which was attributed to barrier lowering due to very high dopant concentrations residing within the gate oxide at the perimeter just under the gate (3). The Varian group (5) had reported charging during implantation was at least partially responsible for gate oxide degradation. This present study was undertaken to provide a systematic characterization of the oxide degradation in order to ultimately provide a satisfactory explanation of the phenomena.It could be postulated that many factors acting either independently or synergistically, are important in causing this edge breakdown effect. For example, these mechanisms may include; gate charging, radiation damage, recoiled atoms, and ion mixing at the gate edge. Over the years, the effect of ion implantation into or through gate oxides has been documented in many studies. Few studi...

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Section: -[3]mentioning

confidence: 76%