A Study on Impact of Leakage Current on Dynamic Power

Rastogi, Ashesh; Ganeshpure, Kunal; Kundu, Sandip

doi:10.1109/iscas.2007.378194

Cited by 4 publications

(1 citation statement)

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“…Leakage dependent on physical parameters of transis variations, and supply voltage fluctuations [1 dependence on input patterns becomes sig 100nm technology [17]. This can be attribute parts of CMOS leakage, namely: a) Sub-Threshold Leakage Sub-threshold leakage occurs when a tra off-state.…”

Section: ) Leakage Power Dependency On Input Pmentioning

confidence: 99%

Power balanced circuits for leakage-power-attacks resilient design

Halak

Murphy

Yakovlev

2015

2015 Science and Information Conference (SAI)

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The continuous rise of static power consumption in modern CMOS technologies has led to the creation of a novel class of security attacks on cryptographic systems. The latter exploits the correlation between leakage current and the input patterns to infer the secret key; it is called leakage power analysis (LPA). The use power-balanced (m-of-n) logic is a promising solution that provides an answer to this problem, such circuits are designed to consume constant amount of power regardless of data being processed. This work evaluates the security of cryptographic circuits designed with this technology against the newly developed LPA. Two forms of LPA are investigated, one is based on differential power analysis (LDPA) and the other based on Hamming weight analysis (LHPA). Simulations performed at 90nm CMOS technology reveal that (m-of-n) circuits are totally resilient to LHPA and have a higher security level against LDPA than standard logic circuits.

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Section: ) Leakage Power Dependency On Input Pmentioning

confidence: 99%