A study on modeling and simulation of Multiple- Gate MOSFETs

Singh, Mandeep Singh Jit; Kumar, Gaurav; Bordoloi, Sushanta; Trivedi, Gaurav

doi:10.1088/1742-6596/759/1/012093

Cited by 13 publications

(4 citation statements)

References 12 publications

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“…GaSb material is used to drain. HfO2 material is used in spacer and SiO2 material used in gate oxide .The nonlocal path band to band tunnelling model [13] was used to model the tunnel in the proposed structure. In accumulation, SRH recombination and band gap narrowing (old slot boom) models are used the device.…”

Section: (B)double Gate Htfetmentioning

confidence: 99%

Performance Analysis of Double Gate Hetero Junction Tunnel Fet

2019

IJITEE

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In this paper, a novel heterojunction tunnel field-effect transistor (HTFET) using Sentaurus technology computer-aided design (TCAD) simulations has been presented. The InAs/GaSb compound materials are used in both single gate heterojunction TFET (SG-HTFET) and Double gate heterojunction TFET (DG-HTFET) with SiO2 gate oxide layer to increase performance of the device.The implemented SG-HTFET and DG-HTFET device are increase the TFET's cross-sectional tunnel area. This result develops the subthreshold swing (SS) by 2.45 times, drive current (ION) is close to 10-6 A/µm, leakage current (IOFF) is close to 10-17 A/µm and also diminish the ambipolarity of the device compared to the TFET.

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Section: (B)double Gate Htfetmentioning

confidence: 99%

Performance Analysis of Double Gate Hetero Junction Tunnel Fet

2019

IJITEE

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“…Enormous research has been carried out in the past few decades to find novel transistors that can be reduced down to the nanoscale regime 1 . Short channel effects (SCEs) are reduced by utilizing several gate transistors 2,3 . Besides the SCEs, the production of junctions is a factor that restricts the transistor's continued growth.…”

Section: Introductionmentioning

confidence: 99%

Surface potential and mobile charge based drain current modeling of double gate junctionless accumulation mode negative capacitance field effect transistor

Yadav,

Rewari,

Pandey

2023

Int J Numerical Modelling

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An analytical drain current model for double gate junctionless accumulation mode negative capacitance field effect transistor (DG‐JAM‐NC‐FET) has been developed, combining the merits of junctionless accumulation mode and negative capacitance effect such as fabrication feasibility, low power dissipation, and reduced degradation in mobility. The novelty manifested in our work is because of the incorporation of the JAM structure in ferroelectric‐based negative capacitance FET. The benefit of JAM over existing FETs is that it combines the benefits of the junctionless transistor (JLT) and conventional FETs. It avoids excessive parasitic resistance due to stronger doping in the source and drain areas, resulting in higher conductivity and better characteristics than JLT. An analytical surface potential and threshold voltage have been developed using Poisson's equation and Landau Khalatnikov's (L‐K) equation. The drain current is then determined by integrating the mobile charge using the Pao–Sah integral. Various critical parameters such as surface potential, gain, capacitance, mobile charge density, drain current, threshold voltage, subthreshold swing, transconductance, and the switching ratio have been assessed extensively by varying ferroelectric layer and channel layer thicknesses, respectively. The ON current increases with the increase in ferroelectric thickness due to the voltage amplification given by the ferroelectric layer, and the switching curve gets steeper. The analytical modeling is done in MATLAB, and its comparison is made with the TCAD numerical simulation. The obtained analytical results and the numerical simulation results correspond well.

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“…On the other hand, numerous gate devices that are electrically controlled by a single gate electrode have emerged, including DG FETs, FinFETs, and Gate All Around (GAA) FETs 14 . These multi-gate architectures developed to improve gate controllability and, to some extent, reduce leakage currents.…”

Section: Introductionmentioning

confidence: 99%

Evolution of type-II hetero-strain cylindrical-gate-all-around nanowire FET for exploration and analysis of enriched performances

Barik

Dhar

Awwad

et al. 2023

Sci Rep

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The incubation of strained nano-system in the form of tri-layered structure as nanowire channel in the cylindrical-gate-all-around (CGAA) FET at 10 nm gate length is developed for the first time to keep abreast with the proposed 3 nm technology node of IRDS 2022. The system installs Type-II hetero-strain alignment in the channel attesting itself as the fastest operating device debasing the SCEs at nano regime. The ultra-thin strained-channel comprises of two cylindrical s-Si wells encompassing s-SiGe barrier in between, which enables improvement of carrier mobility by succumbing of quantum charge carriers in the region. This results in 2D charge centroid creation with cylindrical based circular Nano-system contemplating electrostatic potential difference leading to enriched electric field, current density and transconductance, while the gate-all-around architecture with increased gate controllability lowers leakage current, in the device. The 10 nm strained-channel CGAA astounded havoc ON current enhancements of ~ 20% over 22 nm strained CGAA, 57% over Si CGAA FET and 75% over proposed 3 nm technology node IRDS 2022 are accomplished. Hence, carrier mobility and velocity enriches instituting quasi-ballistic transport through the Nanowire channel, thereby augments in ~ 28% drain current so the 10 nm channel CGAA FET stands as the most suitable and improved device in nano regime.

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A study on modeling and simulation of Multiple- Gate MOSFETs

Cited by 13 publications

References 12 publications

Performance Analysis of Double Gate Hetero Junction Tunnel Fet

Performance Analysis of Double Gate Hetero Junction Tunnel Fet

Surface potential and mobile charge based drain current modeling of double gate junctionless accumulation mode negative capacitance field effect transistor

Evolution of type-II hetero-strain cylindrical-gate-all-around nanowire FET for exploration and analysis of enriched performances

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