A sub-1 Volt 10-bit supply boosted SAR ADC design in standard CMOS

Ay, Suat U.

doi:10.1007/s10470-010-9515-3

Cited by 52 publications

(20 citation statements)

References 24 publications

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“…However, these techniques result in increased circuit complexity, higher power consumption, degraded energy efficiency, or slower operation. In addressing some of these drawbacks, a new mixed-signal design technique called supply boosting (SBT) was proposed [13][14][15]. A new comparator topology has been developed using supply boosting resulting in low-voltage, and energy efficient operations.…”

Section: Open Accessmentioning

confidence: 99%

“…A modified version of the charge pump circuit design technique is proposed and called supply boosting technique (SBT) [13][14][15]. In supply boosted circuits, system supply voltage is boosted locally only once allowing boosted voltages such as clock and supply voltages to drop from their boosted level, V AAB , as shown in Figure 1b.…”

Section: Supply Boosting Technique (Sbt)mentioning

confidence: 99%

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Energy Efficient Supply Boosted Comparator Design

2011

JLPEA

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This paper presents a new mixed-signal design technique called supply boosting technique (SBT) and the design of an energy efficient, sub-1 V supply boosted comparator (SBC) in a standard complementary metal oxide semiconductor (CMOS) process. The selected CMOS process does not allow sub-1 V operation with a wide input range due to high threshold voltage (high-V TH ) of MOS transistors (+0.8 V/−0.9 V). Despite this, the proposed comparator operates sub-1 V supply voltages with input common mode voltage larger than 60% of supply voltage by utilizing a supply boosting technique. The measured power consumption of the supply boosted comparator for 1 V supply was 90 nW and speed was 6500 conversions per second, resulting in 14 pJ per conversion energy efficiency.

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Section: Open Accessmentioning

confidence: 99%

Section: Supply Boosting Technique (Sbt)mentioning

confidence: 99%

Energy Efficient Supply Boosted Comparator Design

2011

JLPEA

Self Cite

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“…Besides, low-voltage operation results in limited common-mode input range, which is important in many high-speed ADC architectures, such as flash ADCs. Many techniques, such as supply boosting methods [2], [3], techniques employing body-driven transistors [4], [5], current-mode design [6] and those using dual-oxide processes, which can handle higher supply voltages have been developed to meet the low-voltage design challenges. Boosting and bootstrapping are two techniques based on augmenting the supply, reference, or clock voltage to address input-range and switching problems.…”

Section: Introductionmentioning

confidence: 99%

High Speed and Low Power Double-Tail Comparator using Switching Transistor

Balla¹,

YKUNTAM²

2014

International Journal of Advanced Research in Computer and Comm

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Abstract:The high speed conversions are needed in the faster analog -to-digital converters. The accuracy of comparators is defined by its power consumption and speed. Many high speed ADCs, such as flash ADCs, require High speed, Low power comparators with small chip area. Conventional dynamic latched comparators suffer from low supply voltages especially when threshold voltage of the devices is not scaled at the same pace as the supply voltages of the modern CMOS process. The proposed comparator System has lower input-referred latch offset voltage and higher load drivability than the conventional dynamic latched comparators. In the dynamic Double tail comparator the simulation in a CMOS technology. In the Proposed dynamic Double tail comparator System both the power consumption and delay time will be significantly reduced. The maximum clock frequency of the proposed comparator can be reduced at modified supply voltages.

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“…On the contrary, applications like capacitance sensors and biosensor readout circuits, high fidelity sound processing systems etc., operate on input signals with frequencies of up to a few kHz but require ADCs of high accuracy in terms of static linearity and dynamic resolution [4][5][6][7][8][9]. A resolution higher than 8-bits is usually required in this case.…”

Section: Introductionmentioning

confidence: 99%

An ultra low die area 8-b ADC and its generic calibration logic

Petrellis

Birbas²

2011

Analog Integr Circ Sig Process

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The 8-bit voltage mode subrange A/D converter described in this paper operates in a mid-input signal frequency range of up to 20 MHz and requires at least an order of magnitude lower die area (0.06 mm 2 ) than other A/D converters with a similar resolution. Moreover, it dissipates only 4.5 mW power and is supported by a calibration logic that is general enough to be used by several other measurement and instrumentation applications that require a real time adjustment of the amplitude and the level of their differential signals. This voltage mode subrange A/D converter architecture is actually an asynchronous two-step A/D converter that is based on a novel integer division operation. The current mode implementation of such an integer divider has already been employed by the authors in an innovative low area/power binary tree A/D conversion architecture. The voltage mode implementation of the integer divider allows the realization of the higher speed and lower power/area subrange A/D converter that is presented in this article.

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A sub-1 Volt 10-bit supply boosted SAR ADC design in standard CMOS

Cited by 52 publications

References 24 publications

Energy Efficient Supply Boosted Comparator Design

Energy Efficient Supply Boosted Comparator Design

High Speed and Low Power Double-Tail Comparator using Switching Transistor

An ultra low die area 8-b ADC and its generic calibration logic

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