A Sub-GHz Wireless Transmitter Utilizing a Multi-Class-Linearized PA and Time-Domain Wideband-Auto I/Q-LOFT Calibration for IEEE 802.11af WLAN

Un, Ka-Fai; Yu, Wei-Han; Cheang, Chak Fong; Qi, Gengzhen; Mak, Pui-In; Martins, Rui P.

doi:10.1109/tmtt.2015.2462815

Cited by 9 publications

(5 citation statements)

References 25 publications

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“…Meanwhile, each block of this work is a standard implementation of corresponding architecture without the latest performance improvement techniques. Additionally, to suppress the local oscillating feedthrough, various methods are proposed by integrating an upsample filter and designing calibration schemes [30][31][32]. All of the above points could be improved in future works.…”

Section: Discussionmentioning

confidence: 99%

A 55 nm CMOS RF Transmitter Front-End with an Active Mixer and a Class-E Power Amplifier for 433 MHz ISM Band Applications

Yuan,

Zhou,

Wang

et al. 2023

Electronics

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In order to meet the increasing demands of wireless communication for ISM bands, a 433 MHz transmitter RF front-end is designed using a 55 nm low-power CMOS technology. The circuits consist of an active mixer, a driver amplifier and a class-E power amplifier (PA). A double-balanced Gilbert active mixer is designed to realize binary phase-shift keying (BPSK) modulation. The driver is used to preamplify the modulated RF signals. The class-E PA adopts a parallel four-branch cascode structure to control the output power level. The load network of the PA is implemented through an off-chip circuit, in which a finite DC-feed inductance load network is selected to reduce the power loss. The mixer and driver are designed with a 1.2 V supply voltage, while the PA is operated at a 1.8 V supply voltage. The area of the chip is 0.206 mm × 0.089 mm, and the measured results show that it achieves a maximum output power of 2.7 dBm, with a total power consumption of 6.72 mW. At a drain efficiency (DE) of 34.5%, an S22 less than −10 dB over the frequency ranges from 393.79 MHz to 455.70 MHz can be measured for the PA. With 192 kbps BPSK data modulated at 433 MHz, the measured EVM is about 0.83% rms.

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Section: Discussionmentioning

confidence: 99%

A 55 nm CMOS RF Transmitter Front-End with an Active Mixer and a Class-E Power Amplifier for 433 MHz ISM Band Applications

Yuan,

Zhou,

Wang

et al. 2023

Electronics

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“…Figure 3 shows simulated voltage waveforms at the drain nodes of the common source transistors and a single‐ended output node when the circuit operates at the 1 dB compression point (P1dB) condition with a 900 MHz input signal. According to the time‐dependent dielectric breakdown condition, the rms voltage across each transistor should not exceed the maximum supply voltage [12]. The maximum dc supply voltages for the 40 nm and 270 nm devices have been specified as 1.1 V and 2.75 V, respectively, in the design manual of the foundry.…”

Section: Circuit Designmentioning

confidence: 99%

“…The authors in [11] mentioned that the ACLR can be improved by adding digital predistortion, harmonic cancelation, g m linearization to attain the required ACLR. Reference [12] describes another design case including a power amplifier and shows a flat error vector magnitude (EVM) response greater than 9 dB to 10 dB back‐off owing to the memory effect of the power amplifier. The authors also applied digital predistortion and improved the EVM and ACLR.…”

Section: Measurementsmentioning

confidence: 99%

“…In particular, the transmit spectrum of 802.11af should be satisfied with the requirement of a 55 dBc adjacent channel leakage ratio (ACLR) [9]. Therefore, the main challenge in the transmitter is the design of a wideband high‐linear operation [10–12]. The linearity of the transmitter is mostly affected at the final stage, which is the output drive amplifier.…”

Section: Introductionmentioning

confidence: 99%

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A dual‐path high linear amplifier for carrier aggregation

Kang

Choi

2020

ETRI Journal

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A 40 nm complementary metal oxide semiconductor carrier-aggregated drive amplifier with high linearity is presented for sub-GHz Internet of Things applications. The proposed drive amplifier consists of two high linear amplifiers, which are composed of five differential cascode cells. Carrier aggregation can be achieved by switching on both the driver amplifiers simultaneously and combining the two independent signals in the current mode. The common gate bias of the cascode cells is selected to maximize the output 1 dB compression point (P1dB) to support high-linear wideband applications, and is used for the local supply voltage of digital circuitry for gain control. The proposed circuit achieved an output P1dB of 10.7 dBm with over 22.8 dBm of output 3rd-order intercept point up to 0.9 GHz and demonstrated a 55 dBc adjacent channel leakage ratio (ACLR) for the 802.11af with −5 dBm channel power. To the best of our knowledge, this is the first demonstration of the wideband carrier-aggregated drive amplifier that achieves the highest ACLR performance.

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“…However, its major goal is to detect the existence of a certain signal, rather than quantify magnitude of the interested signal. After signal has been acquired, least mean square (LMS) is a popular precise estimation metric, usually realized in FPGA [13]. In sum, to our knowledge, no literature has covered on efficient, highly integrated method for HBC spectrum shaping and its corresponding calibration system of low complexity, yet high sensitivity.…”

Section: Introductionmentioning

confidence: 99%

An IM2-free floating current buffer using average power based automatic calibration for IEEE 802.15.6 transmitter

Liu

Yang

et al. 2016

IEICE Electron. Express

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To meet the stringent spectral mask requirement of IEEE 802.15.6, a novel spectral shaping buffer and a new automatic calibration are proposed in this paper. By introducing a floating current into buffer, second order intermodulation product (IM2) is cancelled at output. To calibrate buffer, analog signal processing methods for average power extraction of residual IM2 and accurate quantization are presented, along with error-tolerant decision making logic. A sample human body communication (HBC) transmitter is designed in 0.13 µm CMOS process. Simulation results show spectral mask is suppressed below −120 dBr, satisfying the IEEE 802.15.6 standard specification.

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A Sub-GHz Wireless Transmitter Utilizing a Multi-Class-Linearized PA and Time-Domain Wideband-Auto I/Q-LOFT Calibration for IEEE 802.11af WLAN

Cited by 9 publications

References 25 publications

A 55 nm CMOS RF Transmitter Front-End with an Active Mixer and a Class-E Power Amplifier for 433 MHz ISM Band Applications

A 55 nm CMOS RF Transmitter Front-End with an Active Mixer and a Class-E Power Amplifier for 433 MHz ISM Band Applications

A dual‐path high linear amplifier for carrier aggregation

An IM2-free floating current buffer using average power based automatic calibration for IEEE 802.15.6 transmitter

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