A sub-micron CMOS echo canceller using a DSP cell

Abstract

THIS PAPER WILL DESCRIBE a 45K-gate echo canceller VLSI which was designed automatically b y using standard cell compilation system and was fabricated in 0.8pm CMOS technology. The 45K-gate VLSI with a core-digital signal processor has been integrated into an 11.5mm x 11.8mm chip.In most conventional automatic standard cell approaches, the layout is performed non-hierarchically, using only simple gat? cells irr a bottom-up manner. These approaches often require more chip area and a long turn around time. To solve these problems, a top-down layout system with hierarchy has been developed. In this system, different hierarchical levels o f cells can be automatically placed and wired in a chip layout. The levels are super cell, compiled cell and simple gate cell. .4 super cell is a large functional custom cell and can be compiled by modifying functions and shrinking a physical pattern of an LSI which is already designed and has been confirmed to work. A compiled cell is automatically generated by the cell compiler and consists of bit-word array structure such as RAM, ROM, PLA and data-flow unit. To use the chip area effectively, the routing process is accomplished over the whole chip. Signal nets and power supply nets are automatically wired using triple metal layers. Figure 1 shows the chip compilation flow of the layout system. triple metal layer metallization; Table 1 . The grid pitches of 1 st, 2nd and 3rd metal are 3 ,~m , 4pm and 6pm, respectively. These values are 1.5 times s m d h than those of 1 . 5~ CMOS technologyl. These short channel transistors have been achieved by optimizing the impurity profile in both wells. High-speed operation without the hot carrier effect has been achieved by using sub-micron gate lengths and a low supply voltage. The recommended supply voltage is 3V. The propagation delay time oC these devices at VDD = 3V is estimated to be 1.3 times shorter than that of a 1.2W-inverter at VDD = 5V with f/o = 4.The propagation delay time of the inverter is 0.2ns with f/o = 1; Figure 2.The compilation system and the sub-micron CMOS process have been applied to a 45K-gate echo canceller chip with a core-DSP. Figure 3 shows the block diagram of the echo-canceller. The power dissipation at VDD = 3V is estimated about 1j2.5 of that at VDD = 5V. Thus, the low supply voltage has an ad-The process technology used was 0 . 8~ twin-tub CMOS with -'Takayama, Y., et. al., "A Ins 20R CMOS Gate Array Series