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THIS PAPER will describe a series of three generic arrays of a 20K-gate equivalent CMOS gate array with configurable memory.Features of the technology are twin tub structure, 1.5p gate length for N-channel and 2 . 0 ,~ for P-channel, and three layers of metalization as shown in Table 1. By using this technology, l.Ons propagation delay time is achieved under a typical condition of 2-input NAND gate with fanout 2 and nominal wiring length. The performance of NAND gate and inverter as a function of gate length is shown in Figure 1.As the gate size decreases and the speed performance is improved, gate array becomes the kernal of a digital system. Thus various kinds of high-speed RAM are required to be integrated in the gate array so that the system attains higher performance. For such a requirement three generic arrays with different logic to memory ratios have been developed. Their chip structures are shown in Figure 2 and are summarized in Table 2. Each generic array is separated in 4 quadrants, each of which is a 5K-gate logic or 6Kb memory blo C k .For a highly integrated array, a key point is to minimize the wiring channel area and shorten the wiring length. A three-level metal technology, a double column structure of the basic cell, and a hierarchical design methodology were applied to the development of the series of BOK-gate generic arrays.BIi-gates, it is estimated that a total of 2,100 vertical wiring channels are required for a BOK-gate array. By applying the third metal layer, which is lined vertically in parallel with the first metal, 2100 wiring channels are obtained without any increase of chip size. a conventional single column one for the logic portion of the arrays, as shown in Figure 3. More complicated functional macros arc necessary to realize flexibility and high throughput for a highly integrated logic circuit. A double column structure is suitable for compacting large macro layouts, such as flipflops, counters and ALUs. Consequently, an intensive use of both large macros and a double column structure has made it possible to achieve higher speed operation within functional macros and to reduce the number of inter macro wirings. circuitry is used. The chip consists of four quadrants, and each From our prior experience, designing various gate arrays up to A double column structure has been developed together with To minimize wiring length, a hierarchical structure of logic Chairman: Frank W. Hewlett, Jr. Sandia National Labs.Albuquerque, N M quadrant has lower level blocks and macros. Using the hierarchical structure, functionally related macros are placed together closely, resulting in less total wiring length. The hierarchical structure can also give a excellent prediction of the actual wiring length during the circuit design stage prior to layout.A 6Kb RAM which occupies one quadrant, is composed of four 64w x 24b memory arrays. A 128 word memory is also available by combining two 64w x 24b memory arrays. Typical access time is 15ns for a 64 word dual port RAM. To provide memory array testabi...

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THIS PAPER WILL DESCRIBE a 45K-gate echo canceller VLSI which was designed automatically b y using standard cell compilation system and was fabricated in 0.8pm CMOS technology. The 45K-gate VLSI with a core-digital signal processor has been integrated into an 11.5mm x 11.8mm chip.In most conventional automatic standard cell approaches, the layout is performed non-hierarchically, using only simple gat? cells irr a bottom-up manner. These approaches often require more chip area and a long turn around time. To solve these problems, a top-down layout system with hierarchy has been developed. In this system, different hierarchical levels o f cells can be automatically placed and wired in a chip layout. The levels are super cell, compiled cell and simple gate cell. .4 super cell is a large functional custom cell and can be compiled by modifying functions and shrinking a physical pattern of an LSI which is already designed and has been confirmed to work. A compiled cell is automatically generated by the cell compiler and consists of bit-word array structure such as RAM, ROM, PLA and data-flow unit. To use the chip area effectively, the routing process is accomplished over the whole chip. Signal nets and power supply nets are automatically wired using triple metal layers. Figure 1 shows the chip compilation flow of the layout system. triple metal layer metallization; Table 1 . The grid pitches of 1 st, 2nd and 3rd metal are 3 ,~m , 4pm and 6pm, respectively. These values are 1.5 times s m d h than those of 1 . 5~ CMOS technologyl. These short channel transistors have been achieved by optimizing the impurity profile in both wells. High-speed operation without the hot carrier effect has been achieved by using sub-micron gate lengths and a low supply voltage. The recommended supply voltage is 3V. The propagation delay time oC these devices at VDD = 3V is estimated to be 1.3 times shorter than that of a 1.2W-inverter at VDD = 5V with f/o = 4.The propagation delay time of the inverter is 0.2ns with f/o = 1; Figure 2.The compilation system and the sub-micron CMOS process have been applied to a 45K-gate echo canceller chip with a core-DSP. Figure 3 shows the block diagram of the echo-canceller. The power dissipation at VDD = 3V is estimated about 1j2.5 of that at VDD = 5V. Thus, the low supply voltage has an ad-The process technology used was 0 . 8~ twin-tub CMOS with -'Takayama, Y., et. al., "A Ins 20R CMOS Gate Array Series