A Sub-μW 3–10MHz Stacked Oscillator with a Duty-Cycle Calibrated Level Shifter

Rodrigues, G. C.; Caetano, Diogo; Brito, Diogo; Fernandes, Jorge; Rabuske, Taimur

doi:10.1109/iscas45731.2020.9180389

Cited by 3 publications

(3 citation statements)

References 6 publications

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“…When S 1 is active, the circuit is in the sampling phase, and the sampling capacitor C s is connected to V DD . The resulting charge (Q s ) can be expressed by (1).…”

Section: A Simplified Circuit and Working Principle Overviewmentioning

confidence: 99%

“…As PRs are known for their strong variability, a distributed filter approach is chosen, which works with MOSCAPs being placed between several PRs. This design reduces the impact of non linearity and allows to achieve a large-order filter [1]. For the desired application, there is no need for defining the cut-off frequency too accurately, as the most important requirement lies in keeping its value much lower than the oscillator frequency.…”

Section: B Low-pass Filtermentioning

confidence: 99%

“…Conventional ring oscillators usually target medium to high frequency applications. On the other hand, they may be used as subcircuits of stacked oscillators to generate low frequencies without sacrificing power and maintaining a sub-µW performance at a few MHz [1]. The array of stacked oscillators share the same supply current and proportionally allocate a fraction of the supply voltage for each oscillator cell (osc 1 -osc 4 in Fig.…”

Section: Introductionmentioning

confidence: 99%

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A Temperature-Compensated 57 PPM/°C 10MHz, 2.4μW Stacked Ring Oscillator

Rodrigues

Brito

Busse

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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Ring oscillators are one of the simplest, smallest and most energy-efficient topologies when it comes to clock generation. Being implemented using a chain of digital inverters, their oscillation frequency can be set by the inverters count in the chain and the delay of each inverter. This is an advantage when considering the simplicity and size, however, it is also the cause for high frequency variation with temperature. In this paper we propose an ultra-low power oscillator circuit that exploits a stack of small ring oscillators for supply current reuse and injection locking, which provides phase noise improvement. Frequency stability is achieved through a feedback loop that relies on a frequency-to-voltage converter with improved linearity and reduced temperature sensitivity based on MOS capacitors. Simulation results show that the oscillation frequency changes ±0.4% from 0 to 70ºC (57 ppm/ • C) while consuming 2.4 µW at 10 MHz, with a phase noise of -88.9 dBc/Hz at 100 kHz offset.Index Terms-Frequency to voltage converter, MOSCAPs, ring oscillator, stacked oscillator.

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“…When S 1 is active, the circuit is in the sampling phase, and the sampling capacitor C s is connected to V DD . The resulting charge (Q s ) can be expressed by (1).…”

Section: A Simplified Circuit and Working Principle Overviewmentioning

confidence: 99%

Section: B Low-pass Filtermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A Temperature-Compensated 57 PPM/°C 10MHz, 2.4μW Stacked Ring Oscillator

Rodrigues

Brito

Busse

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

Self Cite

View full text Add to dashboard Cite

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An ASIC Interface for CMUTs-based Biosensors with High Voltage Boosting and Oscillator

Zhao

Barbruni

et al. 2022

2022 IEEE International Symposium on Circuits and Systems (ISCAS)

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A Reconfigurable Single-Supply Multiple-Level Down-Shifter for System-on-Chip Applications

Karimi

Ali

Hassan

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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A novel level down shifter intended for translation of signals with different amplitudes in System-on-Chip (SoC) applications is presented. This new single supply down-shifter architecture, implemented in a 0.35-µm AMS CMOS technology provides multiple reconfigurable levels. A diode connected circuit structure, a current source, five transmission gates, a diodesupercapacitor combination, and input/output buffers are employed to implement this reconfigurable level shifter. The circuit receives a pulse shaped signal with an amplitude of 3.3 V, and provides three different signals with nominal amplitudes of 1.2 V, 1.8 V, and 2.5 V depends on the circuit configuration. The proposed circuit successfully drives a range of capacitive loads between 10 fF and 350 pF. The presented circuit consumes a static and a dynamic power consumptions of 62.37 pW and 108.9μW, respectively from a 3.3V supply, at an operating frequency of 1 MHz and a capacitive load of 10 pF. Post-layout simulation results show that the fall and rise propagation delays of the three configurations are in the range of 0.54 ns-26.5 ns and 11.2 ns-117.2 ns, respectively. It occupies an area of 80 µm×100 µm.

show abstract

A Sub-μW 3–10MHz Stacked Oscillator with a Duty-Cycle Calibrated Level Shifter

Cited by 3 publications

References 6 publications

A Temperature-Compensated 57 PPM/°C 10MHz, 2.4μW Stacked Ring Oscillator

A Temperature-Compensated 57 PPM/°C 10MHz, 2.4μW Stacked Ring Oscillator

An ASIC Interface for CMUTs-based Biosensors with High Voltage Boosting and Oscillator

A Reconfigurable Single-Supply Multiple-Level Down-Shifter for System-on-Chip Applications

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