A submicron CMOS two level metal process with planarization techniques

Fritsch, U.; Higelin, G.; Enders, Gisela; Müller, W.

doi:10.1109/vmic.1988.14177

Cited by 2 publications

(2 citation statements)

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“…In the last few years, the interest in the use of tungsten in multilevel metallization IC technology has grown considerably (1)(2)(3)(4)(5). Tungsten can be used as a diffusion barrier between silicon and aluminum, as a shunting material on gate structures, and for the filling of vias and contact holes (6)(7)(8).…”

Section: Etchbackmentioning

confidence: 99%

“…However, this technique does not planarize structures where gap spacing exceeds twice the deposited film thickness. Alternatively, spin-on planarization techniques (e.g., photoresist, glasses) followed by etchback produce smoothing over larger lateral dimensions (2)(3)(4)(5)(6)(7) to an extent dependent upon the specific pattern geometry and pitch, and the particular properties and thickness of the spun material (8,9). Additionally, low-viscosity spin-on materials often exhibit undesirable properties, such as shrinkage or contamination.…”

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confidence: 99%

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Planarization of ULSI Topography over Variable Pattern Densities

Daubenspeck

DeBrosse

Koburger

et al. 1991

J. Electrochem. Soc.

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Resist etch-back SiO2 planarization involving a pattern density compensation mask is described for line-space patterns of various dimensions extending to half-micron feature sizes. An empirical model is used to describe the positional dependence of planarization film thickness upon feature density within an array pattern. Design considerations related to the usage of the planarization "block mask" are discussed, a suitable etch condition is specified, and the planarization etchback method is used to achieve long-range, or global planarization.

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