2005
DOI: 10.1109/jssc.2005.848172
|View full text |Cite
|
Sign up to set email alerts
|

A surface potential model for predicting substrate noise coupling in integrated circuits

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
4
1

Citation Types

0
15
0

Year Published

2006
2006
2021
2021

Publication Types

Select...
5
2
1

Relationship

1
7

Authors

Journals

citations
Cited by 20 publications
(15 citation statements)
references
References 13 publications
0
15
0
Order By: Relevance
“…Accurate estimation of substrate noise is required for circuit design to reduce the impact of substrate noise and to minimize the area overhead due to noise immunity design. There are many reports about substrate noise, such as measurements of substrate noise on the fabricated chip [1,2,3,4], extraction methods of substrate resistance [5,6], simulation methods of substrate noise [2,3,7,8], and modeling of noise source for fast substrate noise simulation [4].…”
Section: Introductionmentioning
confidence: 99%
See 1 more Smart Citation
“…Accurate estimation of substrate noise is required for circuit design to reduce the impact of substrate noise and to minimize the area overhead due to noise immunity design. There are many reports about substrate noise, such as measurements of substrate noise on the fabricated chip [1,2,3,4], extraction methods of substrate resistance [5,6], simulation methods of substrate noise [2,3,7,8], and modeling of noise source for fast substrate noise simulation [4].…”
Section: Introductionmentioning
confidence: 99%
“…1 (a) resistivity profile. For substrate resistance extraction, the low resistivity substrate is frequently modeled with uniform resistivity for each substrate layer [2,3,5]. However, substrate model with uniform resistivity for each layer cannot accurately extract substrate resistance for specific layout structures.…”
Section: Introductionmentioning
confidence: 99%
“…Therefore knowledge is needed on how to minimize the interference between different circuits and devices on a chip. More specifically, models are needed that can, at the circuit level, predict how much unwanted interaction can occur between different components [2].…”
Section: Introductionmentioning
confidence: 99%
“…Many proposed schemes are macroscopic models such as Boundary Element Methods, utilizing specific Green's functions for solving related equations [2]. Among these, the numerical solution of Laplace equation, based on Finite element or Finite difference methods, (FEM and FDM) have been the most popular [3,4].…”
Section: Introductionmentioning
confidence: 99%
“…2(f), it can be cumbersome to use -----.--superposition since it involves solving a large system of 4 0 0 equations when there are many ground contacts. Instead, we Symbols supefposition model [6] can use results developed by Holm [9]. The resistance, RG, Lines (1) of the distributed ground structure can be determined by [9, p where with no loss of generality, L > W is assumed.…”
Section: A Distributed Ground Contactsmentioning
confidence: 99%