A surrounding gate transistor (SGT) cell for 64/256 Mbit DRAMs

Sunouchi, K.; Takato, H.; Okabe, N.; Yamada, Takashi; Ozaki, T.; Inoue, Sumio; Hashimoto, Kohji; Hieda, K.; Nitayama, A.; Horiguchi, F.; Masuoka, F.

doi:10.1109/iedm.1989.74220

Cited by 43 publications

(13 citation statements)

References 4 publications

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“…Compared with conventional planar MOSFETs, SGTs have several superior characteristics such as high packing density, high current drive capability, and immunity to the short channel effect [1][2][3][4][5][6]. In a cylindrical/surrounding gate MOSFET (CGT/SGT), a rectangular-shaped silicon core in the original SGT has been replaced with a cylindrical silicon core (pillar).…”

Section: Introductionmentioning

confidence: 99%

Two-Dimensional Analytical Model for Deriving the Threshold Voltage of a Short Channel Fully Depleted Cylindrical/Surrounding Gate MOSFET

Suh

2011

JSTS:Journal of Semiconductor Technology and Science

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Section: Introductionmentioning

confidence: 99%

Two-Dimensional Analytical Model for Deriving the Threshold Voltage of a Short Channel Fully Depleted Cylindrical/Surrounding Gate MOSFET

Suh

2011

JSTS:Journal of Semiconductor Technology and Science

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“…[1][2][3][4][5][6][7] The future may see the use of threedimensional (3D) MOSFETs, such as vertically stacked SiNW FETs, [8][9][10][11][12] for high device densities. An asymmetric channel structure is expected for the vertically stacked SiNW FETs because of the fabrication processes.…”

mentioning

confidence: 99%

Electrical characteristics of asymmetrical silicon nanowire field-effect transistors

Sato

Kakushima

Ohmori

et al. 2011

Applied Physics Letters

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This letter reports the electrical characteristics of nonuniform silicon nanowire nFETs with asymmetric source and drain widths. For electrostatic properties, reduced drain-induced barrier lowering (DIBL) is achieved in a device in which the source is wider than the drain. For carrier transport properties, higher values of surface-roughness-limited mobility (l SR ) are obtained in the sample with the wider drain size. Our electrostatic model shows that the concentration of lines of electric force is relaxed near the wider source edge, which results in smaller DIBL. The asymmetric l SR is attributed to the channel surface morphology with (110)-and (100)-faceted surfaces.

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“…A more advanced array transistor approach using surrounding gate transistor (SGT) will be adopted [5,6].…”

Section: Tis/fin/sgt Drammentioning

confidence: 99%

Advanced memory concepts for DRAM and nonvolatile memories

Horiguchi

2006

Solid-State Electronics

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A surrounding gate transistor (SGT) cell for 64/256 Mbit DRAMs

Cited by 43 publications

References 4 publications

Two-Dimensional Analytical Model for Deriving the Threshold Voltage of a Short Channel Fully Depleted Cylindrical/Surrounding Gate MOSFET

Two-Dimensional Analytical Model for Deriving the Threshold Voltage of a Short Channel Fully Depleted Cylindrical/Surrounding Gate MOSFET

Electrical characteristics of asymmetrical silicon nanowire field-effect transistors

Advanced memory concepts for DRAM and nonvolatile memories

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