A Survey of Architectural Techniques for Near-Threshold Computing

Mittal, Sparsh

doi:10.1145/2821510

Cited by 22 publications

(6 citation statements)

References 63 publications

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“…PULP is a RISCV-based open-source platform 5 built on the near-threshold computing paradigm [17]. The ultra-lowpower design allows reaching outstanding energy efficiency, while data-and thread-level parallelism overcome the performance reduction at low operating voltages.…”

Section: Pulp Platformmentioning

confidence: 99%

DNN is not all you need: Parallelizing Non-Neural ML Algorithms on Ultra-Low-Power IoT Processors

Tabanelli¹,

Tagliavini²,

Benini³

2021

Preprint

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Machine Learning (ML) functions are becoming ubiquitous in latency-and privacy-sensitive IoT applications, prompting for a shift toward near-sensor processing at the extreme edge and the consequent increasing adoption of Parallel Ultra-Low Power (PULP) IoT processors. These computeand memory-constrained parallel architectures need to run efficiently a wide range of algorithms, including key Non-Neural ML kernels that compete favorably with Deep Neural Networks (DNNs) in terms of accuracy under severe resource constraints. In this paper, we focus on enabling efficient parallel execution of Non-Neural ML algorithms on two RISCV-based PULP platforms, namely GAP8, a commercial chip, and PULP-OPEN, a research platform running on an FPGA emulator. We optimized the parallel algorithms through a fine-grained analysis and intensive optimization to maximize the speedup, considering two alternative Floating-Point (FP) emulation libraries on GAP8 and the native FPU support on PULP-OPEN. Experimental results show that a target-optimized emulation library can lead to an average 1.61× runtime improvement compared to a standard emulation library, while the native FPU support reaches up to 32.09×. In terms of parallel speedup, our design improves the sequential execution by 7.04× on average on the targeted octa-core platforms. Lastly, we present a comparison with the ARM Cortex-M4 microcontroller (MCU), a widely adopted commercial solution for edge deployments, which is 12.87× slower than PULP-OPEN.

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Section: Pulp Platformmentioning

confidence: 99%

DNN is not all you need: Parallelizing Non-Neural ML Algorithms on Ultra-Low-Power IoT Processors

Tabanelli¹,

Tagliavini²,

Benini³

2021

Preprint

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“…Voltage scaling reduces energy consumption of circuits at the cost of possible errors [Mittal 2015;. For example, reducing SRAM supply voltage saves leakage energy but also increases probability of read upset (flipping of a bit during read operation) and write failure (writing a wrong bit) .…”

Section: Using Voltage Scalingmentioning

confidence: 99%

A Survey of Techniques for Approximate Computing

2016

Self Cite

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Approximate computing trades off computation quality with effort expended, and as rising performance demands confront plateauing resource budgets, approximate computing has become not merely attractive, but even imperative. In this article, we present a survey of techniques for approximate computing (AC). We discuss strategies for finding approximable program portions and monitoring output quality, techniques for using AC in different processing units (e.g., CPU, GPU, and FPGA), processor components, memory technologies, and so forth, as well as programming frameworks for AC. We classify these techniques based on several key characteristics to emphasize their similarities and differences. The aim of this article is to provide insights to researchers into working of AC techniques and inspire more efforts in this area to make AC the mainstream computing approach in future systems.

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“…In the first step to move beyond traditional RAs, MuTARe provides support for drastically lowering the operating voltage beyond the traditional DVFS levels. When doing so, MuTARe can achieve the lowest energy operating point, which is typically found when transistors operate near their threshold voltage range [Mittal 2015] -Near Threshold Computing (NTC). In this challenging operating environment, however, logic elements become significantly more sensitive to fabrication variability and memories more sensitive to errors, making the reliable operation especially tricky [Rahimi et al 2016].…”

Section: Problem Statement and Proposed Solutionmentioning

confidence: 99%

MuTARe: A Multi-Target, Adaptive Reconfigurable Architecture

Brandalero¹

2020

Anais Do Concurso De Teses E Dissertações Da SBC (CTD-SBC 2020)

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With recent changes in transistor scaling trends, the design of all types of processing systems has become increasingly constrained by power consumption. At the same time, driven by the needs of fast response times, many applications are migrating from the cloud to the edge, pushing for the challenge of increasing the performance of these already power-constrained devices. The key to addressing this problem is to design application-specific processors that perfectly match the application's requirements and avoid unnecessary energy consumption. However, such dedicated platforms require significant design time and are thus unable to match the pace of fast-evolving applications that are deployed in the Internet-of-Things (IoT) every day. Motivated by the need for high energy efficiency and high flexibility in hardware platforms, this thesis paves the way to a new class of low-power adaptive processors that can achieve these goals by automatically modifying their structure at run time to match different applications' resource requirements. The proposed Multi-Target Adaptive Reconfigurable Architecture (MuTARe) is based upon a Coarse-Grained Reconfigurable Architecture (CGRA) that can transparently accelerate already-deployed applications, but incorporates novel compute paradigms such as Approximate Computing (AxC) and Near-Threshold Voltage Computing (NTC) to improve its efficiency. Compared to a traditional system of heterogeneous processing cores (similar to ARM's big.LITTLE), the base MuTARe architecture can (without any change to the existing software) improve the execution time by up to $1.3\times$, adapt to the same task deadline with $1.6\times$ smaller energy consumption or adapt to the same low energy budget with $2.3\times$ better performance. When extended for AxC, MuTARe's power savings can be further improved by up to $50\%$ in error-tolerant applications, and when extended for NTC, MuTARe can save further $30\%$ energy in memory-intensive workloads.

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A Survey of Architectural Techniques for Near-Threshold Computing

Cited by 22 publications

References 63 publications

DNN is not all you need: Parallelizing Non-Neural ML Algorithms on Ultra-Low-Power IoT Processors

DNN is not all you need: Parallelizing Non-Neural ML Algorithms on Ultra-Low-Power IoT Processors

A Survey of Techniques for Approximate Computing

MuTARe: A Multi-Target, Adaptive Reconfigurable Architecture

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