A Survey of Cache Bypassing Techniques

Mittal, Sparsh

doi:10.3390/jlpea6020005

Cited by 26 publications

(13 citation statements)

References 77 publications

(184 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For example, while performing multithreading improves core-utilization efficiency, it also increases cache contention. 89 Similarly, Xue et al 22 note that converting the data-layout from AoS to SoA improves vectorization but also reduces the cache hit ratio. Further, since parallel processors allocate larger fraction of their resources to compute logic than the caches, unlike recent high-end CPUs, Phi does not have a large shared last level cache.…”

Section: Tradeoff Between Multithreading and Cachingmentioning

confidence: 98%

A survey on evaluating and optimizing performance of Intel Xeon Phi

Mittal

2020

Concurrency and Computation

Self Cite

View full text Add to dashboard Cite

Summary Intel's Xeon Phi combines the parallel processing power of a many‐core accelerator with the programming ease of CPUs. In this paper, we present a survey of works that study the architecture of Phi and use it as an accelerator for a broad range of applications. We review performance optimization strategies as well as the factors that bottleneck the performance of Phi. We also review works that perform comparison or collaborative execution of Phi with CPUs and GPUs. This paper will be useful for researchers and developers in the area of computer‐architecture and high‐performance computing.

show abstract

Section: Tradeoff Between Multithreading and Cachingmentioning

confidence: 98%

A survey on evaluating and optimizing performance of Intel Xeon Phi

Mittal

2020

Concurrency and Computation

Self Cite

View full text Add to dashboard Cite

show abstract

“…4. By reducing the number of reads/writes from STT-RAM cache by techniques such as cache bypassing [35], both RDE and write errors can be reduced [6]. 5.…”

Section: Stt-ram Read Disturbance Errormentioning

confidence: 99%

A Survey of Soft-Error Mitigation Techniques for Non-Volatile Memories

Mittal

2017

Computers

Self Cite

View full text Add to dashboard Cite

Non-volatile memories (NVMs) offer superior density and energy characteristics compared to the conventional memories; however, NVMs suffer from severe reliability issues that can easily eclipse their energy efficiency advantages. In this paper, we survey architectural techniques for improving the soft-error reliability of NVMs, specifically PCM (phase change memory) and STT-RAM (spin transfer torque RAM). We focus on soft-errors, such as resistance drift and write disturbance, in PCM and read disturbance and write failures in STT-RAM. By classifying the research works based on key parameters, we highlight their similarities and distinctions. We hope that this survey will underline the crucial importance of addressing NVM reliability for ensuring their system integration and will be useful for researchers, computer architects and processor designers.

show abstract

“…Unfortunately, the increase in processor speed has not been complemented by a similar increase in memory speed. To fully realize the potential of the processors, the memory hierarchy must be proficiently utilized [5] [7].…”

Section: Introductionmentioning

confidence: 99%

A Comparative Study of Cache Optimization Techniques and Cache Mapping Techniques

Gupta¹,

Singh²

2017

IJERT

View full text Add to dashboard Cite

For calculation of the processor performance, cache memory has a significant role. Cache replacement policies have a major role in structures that effectively supervise them as processors now require more power with better efficiency along with good performance. Algorithms aiding such replacement policies focus more on assistanting the increased data prerequisites of processors. LRU (Last Recently Used) policy forecasts a re-reference interval and inputs that reveal a different re-reference interval performs poorly under this policy. Performance variance between hypothetical replacement and LRU is large for highly-associative cache as shown by recent studies. The LRU strategy is prone to memory loads where an operational set is bigger than the available size of cache. For improving the performance of the cache other replacement algorithms are designed. This paper presents a lower overhead, high performing cache replacement strategy for processors that utilize the mechanism of LRU replacement and talks about various other techniques as well.

show abstract

A Survey of Cache Bypassing Techniques

Cited by 26 publications

References 77 publications

A survey on evaluating and optimizing performance of Intel Xeon Phi

A survey on evaluating and optimizing performance of Intel Xeon Phi

A Survey of Soft-Error Mitigation Techniques for Non-Volatile Memories

A Comparative Study of Cache Optimization Techniques and Cache Mapping Techniques

Contact Info

Product

Resources

About