A Survey of Chip-level Thermal Simulators

Sultan, Hameedah; Chauhan, Anjali; Sarangi, Smruti R.

doi:10.1145/3309544

Cited by 31 publications

(5 citation statements)

References 78 publications

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“…Implementing the proposed deterministic turbo, or one inspired from it, in a microarchitecture simulator should be relatively straightforward. Thermal step responses can be obtained with open-source software tools for modeling processor power and temperature [16,17]. It should be emphasized that, to simulate the effect of deterministic turbo on clock frequency, one need not simulate true temperature but only the thermal model used by the turbo, including the model's inaccuracies..…”

Section: Discussionmentioning

confidence: 99%

Exploiting Thermal Transients With Deterministic Turbo Clock Frequency

Michaud

2020

IEEE Comput. Arch. Lett.

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Modern microprocessors feature turbo mechanisms that adjust the clock frequency dynamically so as to maximize processor performance under power and temperature limits. However, the documentation for commercial chips rarely provides more than a superficial description of how turbo works. This paper highlights certains aspects of turbo that are not well known outside the industry and that distinguish it from dynamic thermal management. A plausible open-source turbo is proposed and described, extrapolating from the scarce and sparse information that has been disclosed so far.

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Section: Discussionmentioning

confidence: 99%

Exploiting Thermal Transients With Deterministic Turbo Clock Frequency

Michaud

2020

IEEE Comput. Arch. Lett.

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“…The Green's function is a spatial impulse response of the chip, and the thermal solution is constructed by superposition of the impulse responses to the point sources at different locations. It is thus inherently difficult to include boundary conditions (BCs) in thermal simulation of a finite domain [29], [30] or to use Green's function in situations where the power source is close to the edge of the chip [31]. It is also difficult to apply the conventional approach to transient thermal simulation [29], [32].…”

Section: Green's Function Methodsmentioning

confidence: 99%

“…It is thus inherently difficult to include boundary conditions (BCs) in thermal simulation of a finite domain [29], [30] or to use Green's function in situations where the power source is close to the edge of the chip [31]. It is also difficult to apply the conventional approach to transient thermal simulation [29], [32]. The method is however significantly more efficient than the FEM, FVM or FDM because it only considers a single layer where the power sources are generated.…”

Section: Green's Function Methodsmentioning

confidence: 99%

PODTherm-GP: A Physics-Based Data-Driven Approach for Effective Architecture-Level Thermal Simulation of Multi-Core CPUs

Lin

Dowling

Cheng

et al. 2023

IEEE Trans. Comput.

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A thermal simulation methodology derived from the proper orthogonal decomposition (POD) and the Galerkin projection (GP), hereafter referred to as PODTherm-GP, is evaluated in terms of its efficiency and accuracy in a multi-core CPU. The GP projects the heat transfer equation onto a mathematical space whose basis functions are generated from thermal data enabled by the POD learning algorithm. The thermal solution data are collected from FEniCS using the finite element method (FEM) accounting for appropriate parametric variations. The GP incorporates physical principles of heat transfer in the methodology to reach high accuracy and efficiency. The dynamic power map for the CPU in FEM thermal simulation is generated from gem5 and McPACT, together with the SPLASH-2 benchmarks as the simulation workload. It is shown that PODTherm-GP offers an accurate thermal prediction of the CPU with a resolution as fine as the FEM. It is also demonstrated that PODTherm-GP is capable of predicting the dynamic thermal profile of the chip with a good accuracy beyond the training conditions. Additionally, the approach offers a reduction in degrees of freedom by more than 5 orders of magnitude and a speedup of 4 orders, compared to the FEM.

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“…Book [67], TEMPEST [37], Hotspot [101], SESCTherm [86], Power Blurring [124], Intel Docea [31], Survey [103] DT overlap in that they both provide mechanisms for enumerating devices, attaching additional configuration data to devices (which can be used by higher layers of software). Rafael [94] goes into details of the commonalities between ACPI and Device Tree and the convergence between the two standards.…”

Section: Device Tree (Dt)mentioning

confidence: 99%

“…Sarangi et. al [103] presents one of the most comprehensive and updated surveys of thermal estimation and modeling tools. The semiconductor industry has also developed several comprehensive thermal modeling and estimation tools.…”

Section: Thermal Modelingmentioning

confidence: 99%

Energy Efficient Computing Systems: Architectures, Abstractions and Modeling to Techniques and Standards

Muralidhar,

Borovica-Gajic,

Buyya

2020

Preprint

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Computing systems have undergone a tremendous change in the last few decades with several inflexion points. While Moore's law guided the semiconductor industry to cram more and more transistors and logic into the same volume, the limits of instruction-level parallelism (ILP) and the end of Dennard's scaling drove the industry towards multi-core chips. More recently, we have entered the era of domain-specific architectures and chips for new workloads like artificial intelligence (AI) and machine learning (ML). These trends continue, arguably with other limits, along with challenges imposed by tighter integration, extreme form factors and increasingly diverse workloads, making systems more complex to architect, design, implement and optimize from an energy efficiency perspective. Energy efficiency has now become a first order design parameter and constraint across the entire spectrum of computing devices. Many research surveys have gone into different aspects of energy efficiency techniques in hardware and microarchitecture across devices, servers, HPC/cloud, data center systems along with improved software, algorithms, frameworks, and modeling energy/thermals. Somewhat in parallel, the semiconductor industry has developed techniques and standards around specification, modeling/simulation and verification of complex chips; these areas have not been addressed in detail by previous research surveys. This survey aims to bring these domains holistically together, present the latest in each of these areas, highlight potential gaps and challenges, and discuss opportunities for the next generation of energy efficient systems. The survey is composed of a systematic categorization of key aspects of building energy efficient systems -(a) specificationthe ability to precisely specify the power intent, attributes or properties at different layers (b) modeling and simulation of the entire system or subsystem (hardware or software or both) so as to be able to experiment with possible options and perform what-if analysis, (c) techniques used for implementing energy efficiency at different levels of the stack, (d) verification techniques used to provide guarantees that the functionality of complex designs are preserved, and (e) energy efficiency standards and consortiums that aim to standardize different aspects of energy efficiency, including cross-layer optimizations.CCS Concepts: • Hardware → Power and energy.

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A Survey of Chip-level Thermal Simulators

Cited by 31 publications

References 78 publications

Exploiting Thermal Transients With Deterministic Turbo Clock Frequency

Exploiting Thermal Transients With Deterministic Turbo Clock Frequency

PODTherm-GP: A Physics-Based Data-Driven Approach for Effective Architecture-Level Thermal Simulation of Multi-Core CPUs

Energy Efficient Computing Systems: Architectures, Abstractions and Modeling to Techniques and Standards

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