A Survey of fault models and fault tolerance methods for 2D bus-based multi-core systems and TSV based 3D NOC many-core systems

Shashikiran, Venkatesha,; Parthasarathi, Ranjani

doi:10.48550/arxiv.2203.07830

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“…Usually, a TSV substrate is fabricated mainly by etching through holes in a silicon substrate, and by filling the holes with a conductive material such as Cu, W, and doped polysilicon. In the IC field, TSVs can be used for complementary metal-oxide semiconductor (CMOS) image sensors, SiGe power amplifiers, 3D stacked memory devices, and field-programmable gate array (FPGA) chip integration [ 1 , 2 , 3 ]. The application of TSVs in the IC field can reduce the size of devices, improve signal transmission, and can even address the manufacturing challenges of large chips.…”

Section: Introductionmentioning

confidence: 99%

Process Optimization and Performance Evaluation of TSV Arrays for High Voltage Application

Feng

Zeng

et al. 2022

Micromachines

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In order to obtain high-quality through-silicon via (TSV) arrays for high voltage applications, we optimized the fabrication processes of the Si holes, evaluated the dielectric layers, carried out hole filling by Cu plating, and detected the final structure and electric properties of the TSVs. The Si through-hole array was fabricated in an 8-inch Si substrate as follows: First, a blind Si hole array was formed by the Si deep reactive etching (DRIE) technique using the Bosch process, but with the largest width of the top scallops reduced to 540 nm and the largest notch elimidiameternated by backside grinding, which also opens the bottom ends of the Si blind holes and forms 500-μm-deep Si through holes. Then, the sidewalls of the Si holes were further smoothed by a combination of thermal oxidation and wet etching of the thermal oxide. The insulating capability of the dielectric layers was evaluated prior to metal filling by using a test kit. The metal filling of the through holes was carried out by bottom-up Cu electroplating and followed by annealing at 300 °C for 1 h to release the electroplating stress and to prevent possible large metal thermal expansion in subsequent high-temperature processes. The TSV arrays with different hole diameters and spacing were detected: no visible defects or structure peeling was found by scanning electron microscopy (SEM) observations, and no detectable interdiffusion between Cu and the dielectric layers was detected by energy dispersive X-ray (EDX) analyses. Electric tests indicated that the leakage currents between two adjacent TSVs were as low as 6.80 × 10−10 A when a DC voltage was ramped up from 0 to 350 V, and 2.86 × 10−9 A after a DC voltage was kept at 100 V for 200 s.

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Section: Introductionmentioning

confidence: 99%