A Survey of Neural Front End Amplifiers and Their Requirements toward Practical Neural Interfaces

Abstract

When designing an analog front-end for neural interfacing, it is hard to evaluate the interplay of priority features that one must upkeep. Given the competing nature of design requirements for such systems a good understanding of these trade-offs is necessary. Low power, chip size, noise control, gain, temporal resolution and safety are the salient ones. There is a need to expose theses critical features for high performance neural amplifiers as the density and performance needs of these systems increases. This review revisits the basic science behind the engineering problem of extracting neural signal from living tissue. A summary of architectures and topologies is then presented and illustrated through a rich set of examples based on the literature. A survey of existing systems is presented for comparison based on prevailing performance metrics.

Polymer-CMOS Hybrid Neural Probes for Large-Scale Neuro-Electronic Interfacing

“…Despite the numerous neural amplifier related publications in the recent years, as summarized in [4], few authors consider their large-scale integration into image-sensor style arrays. Capacitive feedback operational amplifiers remain among most popular designs.…”

“…The chip design presented in this work ( Figure 2) attempts to tackle these drawbacks in several ways. Its design emulates a single image-sensor row with 256 "pixels" in which the photodiode input is replaced by simple near-threshold inverter amplifier similar to solution proposed in [4], except the input is DC-coupled and an auxiliary input is provided for offset compensation signal which is broadcast from an external DAC. Outputs are multiplexed using inverter buffer amplifiers, which are switched into virtual ground.…”

Acquisition of Neural Action Potentials Using Rapid Multiplexing Directly at the Electrodes

“…While this approach offers simple solutions to many of the technical issues involved in acquiring neural signals, the resulting silicon chip area per channel is too large to support thousands of electrodes and beyond without dominating the size and form factor of a fully implantable microsystem. Progress has been made in reducing the size of traditional acquisition electronics (e.g., there are >2000 articles listed under “neural amplifier” in the Inspec database at the time of this writing), but state-of-the-art designs still typically result in 0.04–0.1 mm 2 of chip area per electrode channel (10–25 channels/mm 2 ) [ 17 ].…”

“…To the authors’ best knowledge, this paper presents the first in vivo demonstration of a rapidly multiplexed neural recording system without preamplification, designed for high-impedance, penetrating microelectrode arrays that provide measurements of action potentials (APs). Time division multiplexing is often used after amplification to reduce ADC area [ 17 , 20 , 21 , 22 , 23 ] ( Figure 1 a), and has also been used for serialized analog communication in neural recording systems [ 24 , 25 , 26 ]. However, these prior works all use multiplexing after amplification, which does not reduce the area of the amplifiers and thus has limited benefit.…”

Integrated neural interfaces

“…Key challenges are i) the scale of electronics required to enable highly functional systems with many channels, and ii) guaranteeing that integrated neural interfaces can last in implanted environments for long periods of time without suffering failures from packaging, wires, and bio-response. These challenges still exist despite extensive work on neural interface electronics [14]- [16], as well as monolithically integrated CMOS-compatible silicon electrode arrays [7], [12], and is reflected by the lack of publications that demonstrate chronic operation of integrated neural interfaces. For the purposes of this discussion, we will define chronic to imply usability over periods of at least several months, without surgical revision.…”