A survey of spintronic architectures for processing-in-memory and neural networks

Umesh, Sumanth; Mittal, Sparsh

doi:10.1016/j.sysarc.2018.11.005

Cited by 47 publications

(17 citation statements)

References 36 publications

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“…There are various spintronic devices like spin-valve [240], MTJ [81,[241][242][243][244][245], ferroelectric tunnel junction (FTJ) [246][247][248], domain wall [249][250][251][252][253][254][255][256][257], Skyrmion [258][259][260][261]and all spin logic (ASL) devices [262][263][264][265][266][267][268][269], etc. have been reported in the literature.…”

Section: Hybrid Cmos/mtj Circuitsmentioning

confidence: 99%

From MTJ Device to Hybrid CMOS/MTJ Circuits: A Review

et al. 2020

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Spintronics is one of the growing research areas which has the capability to overcome the issues of static power dissipation and volatility suffered by the complementary metal-oxide-semiconductor (CMOS) industry. Magnetic tunnel junction (MTJ), one of the prominent spintronic devices, is not only used to develop the fully non-volatile-logic (NV-L) but combines magnetism and electronics to develop next-generation NVmemory (NV-M) and hybrid CMOS/MTJ circuits. To be specific towards hybrid CMOS/MTJ circuits, the fabrication of first hybrid full-adder in 2009, fabrication of MTJ based 240-tile NV-field programmable gate array (NV-FPGA) chip in 2013, fabrication of a 3000-6-input-LUTs based NV-FPGA chip in 2015, fabrication of MTJ based NV-logic-in-memory-large scale integration (NV-LIM-LSI) in 2017 and recently the fabrication of a full hybrid magnetic/CMOS System on Chip (SoC) under EU GREAT Project in 2019 has strengthened the belief and motivated the researcher to be continued in this domain. This review article aims to provide the complete design flow of hybrid CMOS/MTJ circuits developed using one of the fab compatible MTJ spintronic devices and its integration with conventional CMOS logic. The broad coverage of the article is MTJ construction, its switching mechanisms, a brief history of various compact models, reliability issues, and the concept of logic-in-memory (LIM) architecture. Finally, the article concludes with the challenges and future prospects of hybrid CMOS/MTJ circuits, which will motivate people in academia to cultivate research in this domain and industry to realize the prototype for a wide range of potential applications.

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Section: Hybrid Cmos/mtj Circuitsmentioning

confidence: 99%

From MTJ Device to Hybrid CMOS/MTJ Circuits: A Review

et al. 2020

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“…This work mechanism obviously deviates from that of the biological brain that has data processing and storage taking place at the same place. To address this issue, considerable research enthusiasm has been switched to the realization of ANNs using hardware devices, particularly in the form of non-volatile memories (NVMs) (Howard et al, 2014;Ni et al, 2019;Oh et al, 2019;Umesh and Mittal, 2019;Choi et al, 2020). NVMs families including ferroelectric random-access memory, magnetic random-access memory, phase-change random access memory (PCRAM), and resistive random-access memory, were initially devised to replace static random-access memory and dynamic random-access memory for future memory devices (Zhang et al, 2020).…”

Section: Introductionmentioning

confidence: 99%

Impact of Thermal Boundary Resistance on Thermoelectric Effects of the Blade-Type Phase-Change Random Access Memory Device

Lian

Gao

et al. 2022

Front. Mater.

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Phase-change random access memory (PCRAM) is widely regarded as one of the most promising candidates to replace Flash memory as the next generation of non-volatile memories due to its high-speed and low-power consumption characteristics. Recent advent of the blade-type PCRAM with low programming current merit further confirms its prospects. The thermoelectric effects existing inside the PCRAM devices have always been an important factor that determines the phase-transformation kinetics due to a fact that it allows PCRAM to have electric polarity dependent characteristics. However, the potential physics governing the thermoelectric effects for blade-type PCRAM device still remains vague. We establish a three-dimensional (3D) electro-thermal and phase-transformation model to study the influences of thermal boundary resistance (TBR) and device scaling on the thermoelectric effects of the blade-type PCRAM during its “RESET” operation. Our research shows that the presence of TBR significantly improves the electric polarity-dependent characteristics of the blade-type PCRAM, and such polarity-dependent characteristic is found immune to the scaling of the device. It is therefore possible to optimize the thermoelectric effects of the blade-type PCRAM through appropriately tailoring the TBR parameters, thus further lowering resulting power consumption.

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“…For example, various hybrid circuits have been developed such as non-volatile magnetic adder [9]- [12], non-volatile magnetic decoder [13], non-volatile logic gates [14], magnetic flip-flop [15]- [19], magnetic look up table [20]- [23] for reprogrammable logic circuits and recently polymorphic gate module [24]. There are various circuit and their applications that are also developed using many other spintronic devices, such as spin valves [7], [25], [26], ferroelectric tunnel junctions (FTJs) [27]- [29], domain wall (DW) based magnetic nano wires [30]- [38], all spin logic (ASL) based devices [39]- [41], SPIN-transistors [7], [25], [26], 3-D magnetic ratchet etc., [25], [26], [42]. All these spintronic devices exploit the spin degree of freedom along with the charge on the electrons.…”

Section: Introductionmentioning

confidence: 99%

A Novel Low Power and Reduced Transistor Count Magnetic Arithmetic Logic Unit Using Hybrid STT-MTJ/CMOS Circuit

2020

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One of the major concern for CMOS technology is the increase in power dissipation as the technology node lowers down to deep submicron region. Magnetic tunnel junction (MTJ) working on Spin transfer torque (STT) switching mechanism is recognized as one of the most promising spintronic device for post CMOS era due to its non-volatility, high speed, high endurance, CMOS compatibility and mainly the low power dissipation which can offer the solutions for the problems posed by existing CMOS technology. We have proposed a novel logic-in-memory (LIM) architecture of magnetic arithmetic logic unit (P-MALU) based on hybrid STT-MTJ/CMOS circuits. Simulation results reveal that there is significant reduction in the total power dissipation and transistor count of arithmetic unit by 28.44% and 29.16% compared to double pass transistor logic based clocked CMOS ALU design (DPTL-C 2 MOS-ALU), while 58.87% and 45.16% to modified magnetic arithmetic logic unit (M-MALU) respectively. Reduction in average power dissipation for logical unit is 37.61% and 52.55% along with 47.22% and 42.42% fewer transistors than DPTL-C 2 MOS-ALU and M-MALU design respectively. Monte-Carlo(MC) simulation is then performed by incorporating process and mismatch variations for CMOS and extracted parameters of MTJ, to study the behavior of DPTL-C 2 MOS-ALU, M-MALU and P-MALU designs in terms of power dissipation. All the simulation results reveal that the P-MALU is superior than other two ALU designs in terms of power dissipation, delay and device count. Further, the P-MALU circuit is extended for 4-bits arithmetic operations. Electrical simulations are performed to verify the functionality of the design for higher bit operations which demonstrates the feasibility of the proposed design in VLSI circuits.

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A survey of spintronic architectures for processing-in-memory and neural networks

Cited by 47 publications

References 36 publications

From MTJ Device to Hybrid CMOS/MTJ Circuits: A Review

From MTJ Device to Hybrid CMOS/MTJ Circuits: A Review

Impact of Thermal Boundary Resistance on Thermoelectric Effects of the Blade-Type Phase-Change Random Access Memory Device

A Novel Low Power and Reduced Transistor Count Magnetic Arithmetic Logic Unit Using Hybrid STT-MTJ/CMOS Circuit

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