A survey of SRAM-based in-memory computing techniques and applications

Mittal, Sparsh; Verma, Gaurav; Kaushik, Brajesh Kumar; Khanday, Farooq Ahmad

doi:10.1016/j.sysarc.2021.102276

Cited by 50 publications

(5 citation statements)

References 71 publications

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“…Moreover, it has been pointed out the need to use software tools that can facilitate the task of modeling micro-threaded multi-core architectures, as well as simplify the process of developing and debugging applications for such systems. In this work, it is also considered the possibility of improving the performance of multi-core systems by means of optimizing the operation of cache memory and the control of data flow [26,27]. This study is an important contribution to the development of the field of multi-core system modeling and may be useful for the development of more efficient and productive computing systems in the future.…”

Section: Discussionmentioning

confidence: 99%

Accelerating Code Assembly: Exploiting Heterogeneous Computing Architectures for Optimization

Karyonov

2023

ISI

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Amid rapid technological advancements, the efficient optimization of software code assembly and compilation is paramount to the swift and reliable functioning of highperformance computing systems. This study investigates the potential for boosting code assembly speed by exploiting various computing architectures. The adopted methodology encompasses system analysis, examination of diverse computer system architectures, and the application of optimization and resource management techniques to enhance the assembly and compilation of program codes effectively. The paper delves into the evolution of computer architecture and underscores the importance of machine code, elucidating their impacts on IT development. Key areas of study include mobile object tracking, cache memory-based architectures, and GPU inference mechanisms for neural networks. The criticality of expertise, security, and contextual understanding when adopting these technologies is also emphasized. The findings from this study could catalyze the inception of novel code assembly technologies, thereby optimizing computing efficiency and expediting software development. Consequently, these advancements could diminish the time required for program creation and launch, thereby elevating industry productivity. The practical significance of this research stems from its potential application in accelerating code assembly.

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Section: Discussionmentioning

confidence: 99%

Accelerating Code Assembly: Exploiting Heterogeneous Computing Architectures for Optimization

Karyonov

2023

ISI

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“…Cache memory design for single-bit architecture comprises CWD, 6T-SRAM, and CDSA, as shown in Figure 11 [70]. CWD, 6T-SRAM, CDSA, CTDSA, and VLSA as shown in Figure :11, Figure 12, and Figure 13, respectively [71].…”

Section: Functional Block Diagram Of Single-bit 6t-sram Sa Architecturementioning

confidence: 99%

Security and Privacy of Blockchain-Based Single-Bit Cache Memory Architecture for IoT Systems

et al. 2022

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This paper provides an overview of blockchain technology's security and privacy features, as well as an overview of IoT-based cache memory and single-bit six transistor static random-access memory cell sense amplifier architecture. Each chip's memory is used for recorded as blocks, which are encrypted and used as a blockchain for other memory devices. The architectures comprise of the circuit of write driver, six transistor static random access memory cells, and sense amplifiers such as current differential sense amplifier, charge transfer differential sense amplifier, and voltage latch sense amplifier. Furthermore, different parameters such as the number of transistors, sensing delay, and power consumption have been analyzed for varying resistance values (i.e., R=42.3 and R=42.3K ). Apart from that, power reduction techniques such as dual sleep, forced stack, sleep transistor, and sleep stack are used to optimize power consumption. These power reduction techniques are applied over different blocks of architecture, such as six transistors static random access memory cell and sense amplifier to optimize power consumption of the architecture. The conclusion arises that a single-bit six transistor static random access memory cell with power reduction dual sleep technique voltage latch sense amplifier with power reduction dual sleep technique in architecture consumes 11.65µW of power and has 33 transistors which are lowest from other architectures.INDEX TERMS Circuit of write driver (CWD), sense amplifier (SA), current differential sense amplifier (CDSA), charge transfer differential sense amplifier (CTDSA), voltage latch sense amplifier (VLSA), six transistor static random-access memory (6T-SRAM).

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“…Computational storage devices make it possible to run software within the storage device, offloading the CPU, memory and busses from such a burden [52]. In-memory computing makes it possible to have computing power within the memory array [53] avoiding data transfers between memory and CPU.…”

Section: Hardware a New Memory And Storage Technologiesmentioning

confidence: 99%

The Lannion report on Big Data and Security Monitoring Research

d’Orazio

Agoun

Bossert

et al. 2022

2022 IEEE International Conference on Big Data (Big Data)

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During the last decade, big data management has attracted increasing interest from both the industrial and academic communities. In parallel, Cyber Security has become mandatory due to various and more intensive threats. In June 2022, a group of researchers has met to reflect on their community's impacts on current research challenges. In particular, they have considered four dimensions: (1) dedicated systems being data processing and analytic platforms or time series management systems; (2) graphs analytics and distributed computation; (3) privacy; and (4) new hardware.

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A survey of SRAM-based in-memory computing techniques and applications

Cited by 50 publications

References 71 publications

Accelerating Code Assembly: Exploiting Heterogeneous Computing Architectures for Optimization

Accelerating Code Assembly: Exploiting Heterogeneous Computing Architectures for Optimization

Security and Privacy of Blockchain-Based Single-Bit Cache Memory Architecture for IoT Systems

The Lannion report on Big Data and Security Monitoring Research

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