A survey of techniques for improving energy efficiency in embedded computing systems

Mittal, Sparsh

doi:10.1504/ijcaet.2014.065419

Cited by 135 publications

(45 citation statements)

References 119 publications

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“…It's also defined as a computing system which is designed for specific control functions and is embedded as part of the complete device which may include hardware and mechanical parts [3].…”

Section: A Embedded Systems 1) Definitionsmentioning

confidence: 99%

Using a Cluster for Securing Embedded Systems

Lmimouni¹,

Boukhdir²,

Medromi³

et al. 2016

ijacsa

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Abstract-In today's increasingly interconnected world, the deployment of an Intrusion Detection System (IDS) is becoming very important for securing embedded systems from viruses, worms, attacks, etc. But IDSs face many challenges like computational resources and ubiquitous threats. Many of these challenges can be resolved by running the IDS in a cluster to allow tasks to be parallelly executed. In this paper, we propose to secure embedded systems by using a cluster of embedded cards that can run multiple instances of an IDS in a parallel way. This proposition is now possible with the availability of new lowpower single-board computers (Raspberry Pi, BeagleBoard, Cubieboard, Galileo, etc.). To test the feasibility of our proposed architecture, we run two instances of the Bro IDS on two Raspberry Pi. The results show that we can effectively run multiple instances of an IDS in a parallel way on a cluster of new low-power single-board computers to secure embedded systems.

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Section: A Embedded Systems 1) Definitionsmentioning

confidence: 99%

Using a Cluster for Securing Embedded Systems

Lmimouni¹,

Boukhdir²,

Medromi³

et al. 2016

ijacsa

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“…The scheme of dynamic voltage and frequency scaling (DVFS) scales and clock frequency (henceforth called ) together in order to obtain the best throughput under a given power budget or to save power for a given throughput requirement [1]. 3 The reliable operating region Operational reliability depends on the system platform including various hardware-related design-time and runtime decisions as well as applications and their requirements.…”

Section: Introductionmentioning

confidence: 99%

“…Conversely, increasing causes an increase of temperature, accelerates aging and the probability of breakdowns [7]. This leads to min ≤ ≤ max ( 1 ) An execution may require more than a certain level of throughput to be meaningful [8]. This leads to…”

Section: Introductionmentioning

confidence: 99%

Voltage, Throughput, Power, Reliability, and Multicore Scaling

et al. 2017

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ARM 1 AbstractParallelization has been used to maintain a reasonable balance between energy consumption and performance in computing platforms especially in modern multi-and many-core systems. This paper studies the interplay between performance and energy, and their relationships with parallelization scaling in the context of the reliable operating region, focusing on the effectiveness of parallelization scaling in throughput-power tradeoffs. Theoretical and experimental explorations show that a meaningful cross-platform analysis of this interplay can be achieved using the proposed method of binormalization of the ROR. The concept of this interplay is captured in an online tool for finding optimal operating points. IntroductionIn digital CMOS circuits, a higher supply voltage (called henceforth) usually permits a higher operating (clock) frequency for capacitive load-balancing, and hence a higher throughput, given the same hardware platform. The scheme of dynamic voltage and frequency scaling (DVFS) scales and clock frequency (henceforth called ) together in order to obtain the best throughput under a given power budget or to save power for a given throughput requirement [1].It is possible to increase system throughput for a given power limit, or to reduce power whilst maintaining throughput, by combining DVFS with parallelization or scaling to multiple computation units if the computation can be parallelized [2]. A major challenge for the precise analysis of the effectiveness of using parallelization for these goals is to determine the parallelizability of any particular execution, which is related to complex issues such as software and hardware architecture details and must be modelled on a per-execution basis [3]. Another challenge is that quantitative studies of power and/or throughput improvements for any DVFS decision need complicated executiondependent models [4]. This paper explores the interplay between DVFS and parallelization scalability with respect to performance and power. The interplay is captured using the concept of a reliable operating region (ROR), which can be established from the knowledge of system reliability through experiments or simulations. The ROR therefore provides containment for platform and application specifics, hence helping to make the further analysis steps generic.The focus of this paper is the effectiveness of parallelization scaling, the latter denoted as .The ROR-based method can explore across the entire voltage range of a platform, from subthreshold to super-threshold regions. The explorations and models presented in this paper confirm and explain the general view that combined DVFS and parallelization scaling produces the best advantage when is scaled down to near-threshold voltages. This is known as near-threshold

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“…The amount of power/energy required by these computing systems may not be accessible every time, due to infrastructure unavailability. Also the cost of running the hardware may outrun the cost of owning the hardware platform [1]. To address this issue the Scientific computing community are trying to build computer systems and applications that consume less energy.…”

Section: Introductionmentioning

confidence: 99%

Power Optimization of CFD Applications on Heterogeneous Architectures

Ahmed¹,

Khan²,

Ahmed³

et al. 2017

IJCA

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Computational fluid dynamics (CFD) is widely used by the scientific computing community to solve various fluid flow problems. High performance computing (HPC) enable faster CFD simulations with higher solution accuracies. Many CFD applications are run on multicore and multiprocessor platforms and are being increasingly ported to run on computational accelerators such as graphical processing units (GPUs) to increase the performance. The increase of computational power is necessary to allow faster computing, which in turn increases the power consumption. The issue of the power consumption has to be addressed, particularly in applications such as CFD, where the simulations may need to be executed iteratively for a large number of times, each iteration taking a large amount of time, in order to obtain appropriately accurate results. Poweraware computing is concerned with devising energy efficient methods. Techniques such as Dynamic voltage and frequency scaling (DVFS) and offlining can be used to reduce power consumption and increase the energy efficiency of applications. In this paper, we present a combination of these techniques and apply to CFD applications running on heterogeneous architectures. We reduce the overall power consumption with a small performance loss. Precisely, for DVFS, we save 4% to 23.5% of energy with a performance loss of 0.6% to 9.8%. Similarly, for online-offline mode, we save 22% of energy with a performance loss of 0.3%.

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A survey of techniques for improving energy efficiency in embedded computing systems

Cited by 135 publications

References 119 publications

Using a Cluster for Securing Embedded Systems

Using a Cluster for Securing Embedded Systems

Voltage, Throughput, Power, Reliability, and Multicore Scaling

Power Optimization of CFD Applications on Heterogeneous Architectures

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