A survey of techniques for architecting TLBs

Mittal, Sparsh

doi:10.1002/cpe.4061

Cited by 25 publications

(10 citation statements)

References 114 publications

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“…They observe that a load instruction that misses in caches incurs 115× larger energy than an add operation; thus, data movement energy is much higher than the energy of arithmetical and logical unit (ALU) operations. Due to this, a large fraction of total energy is consumed in moving data across different levels in memory hierarchy . The data movement energy is especially high for web browsers.…”

Section: Processor Architecture Level Techniquesmentioning

confidence: 99%

“…Due to this, a large fraction of total energy is consumed in moving data across different levels in memory hierarchy. 93 The data movement energy is especially high for web browsers. In fact, mobile processor energy is the same while (1) performing arithmetic operations under full utilization and (2) performing only data movement and mostly remaining idle.…”

Section: Getting Insights Into Browser Applications' Characteristicsmentioning

confidence: 99%

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A survey of techniques for improving efficiency of mobile web browsing

Mittal

Mattela

2019

Concurrency and Computation

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Summary Mobile web traffic has now surpassed the desktop web traffic and has become the primary means for service providers to reach out to the billions of end users. Due to this trend, optimization of mobile web browsing (MWB) has gained significant attention. In this paper, we present a survey of techniques for improving the efficiency of web browsing on mobile systems, proposed in the last 6‐7 years. We review the techniques from both the networking domain (eg, proxy and browser enhancements) and the processor architecture domain (eg, hardware customization and thread‐to‐core scheduling). We organize the research works based on key parameters to highlight their similarities and differences. Beyond summarizing the recent works, this survey aims to emphasize the need of architecting for MWB as the first principle, instead of retrofitting for it.

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Section: Processor Architecture Level Techniquesmentioning

confidence: 99%

Section: Getting Insights Into Browser Applications' Characteristicsmentioning

confidence: 99%

A survey of techniques for improving efficiency of mobile web browsing

Mittal

Mattela

2019

Concurrency and Computation

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“…With priority encoding, output of TCAM is the highest prioritized result. TCAM is widely uses in networking routers such as translations-look-aside buffers (TLBs) [3] caches in microprocessors, database accelerators in big data analytics [4] and in pattern recognition [5].…”

Section: Introductionmentioning

confidence: 99%

Efficient TCAM design based on dual port SRAM on FPGA

Triet

Ngo

Trinh

et al. 2021

IJEECS

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<span><span>Ternary content addressable memory (TCAM) is a memory that allows high speed searching for data. Not only it is acknowledged as associative memory/storage but also TCAM can compare input searching content (key) against a collection of accumulated data and return the matching address which compatible with this input search data. SRAM-based TCAM utilizes and allocates blocks RAM to perform application of TCAM on FPGA hardware. This paper presents a design of 480×104 bit SRAM-based TCAM on altera cyclone IV FPGA. Our design achieved lookup rate over 150 millions input search data and update speed at 75 million rules per second. The architecture is configurable, allowing various performance trade-offs to be exploited for different ruleset characteristics</span>.</span>

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“…Further, by virtue of being an open-source tool, it facilitates reproducible research and easy extension of the tool for many more usage scenarios than those discussed in the paper. For example, apart from modeling standard caches, DESTINY can also model assist structures (e.g., victim cache, write-buffer, tag-only caches) and the translational look aside buffer (TLB) [27] designed with different memory technologies. We believe that DESTINY will be a useful tool in architecture and system-level studies and will assist researchers, designers and technical professionals.…”

Section: Introductionmentioning

confidence: 99%

DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability

Mittal

Wang

Vetter

2017

JLPEA

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Abstract:To enable the design of large capacity memory structures, novel memory technologies such as non-volatile memory (NVM) and novel fabrication approaches, e.g., 3D stacking and multi-level cell (MLC) design have been explored. The existing modeling tools, however, cover only a few memory technologies, technology nodes and fabrication approaches. We present DESTINY, a tool for modeling 2D/3D memories designed using SRAM, resistive RAM (ReRAM), spin transfer torque RAM (STT-RAM), phase change RAM (PCM) and embedded DRAM (eDRAM) and 2D memories designed using spin orbit torque RAM (SOT-RAM), domain wall memory (DWM) and Flash memory. In addition to single-level cell (SLC) designs for all of these memories, DESTINY also supports modeling MLC designs for NVMs. We have extensively validated DESTINY against commercial and research prototypes of these memories. DESTINY is very useful for performing design-space exploration across several dimensions, such as optimizing for a target (e.g., latency, area or energy-delay product) for a given memory technology, choosing the suitable memory technology or fabrication method (i.e., 2D v/s 3D) for a given optimization target, etc. We believe that DESTINY will boost studies of next-generation memory architectures used in systems ranging from mobile devices to extreme-scale supercomputers. The latest source-code of DESTINY is available from the following git repository: https://bitbucket.org/sparsh_mittal/destiny_v2.

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A survey of techniques for architecting TLBs

Cited by 25 publications

References 114 publications

A survey of techniques for improving efficiency of mobile web browsing

A survey of techniques for improving efficiency of mobile web browsing

Efficient TCAM design based on dual port SRAM on FPGA

DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability

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