A Survey of Techniques for Modeling and Improving Reliability of Computing Systems

Mittal, Sparsh; Vetter, Jeffrey S.

doi:10.1109/tpds.2015.2426179

Cited by 71 publications

(45 citation statements)

References 114 publications

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“…However, through WDEs, a particular cell can be attacked by writing to many of its neighbors. Also, crossing of the WRE limit due to repeated writes leads to hard errors (i.e, failure of the memory cell) in NVMs, whereas WDE leads to soft errors (i.e., flipping of the bit) [47]. Since flipping of the stored value is likely to get unnoticed more easily than the failure of the memory, WDE-induced attacks are more difficult to detect.…”

Section: Conclusion and Future Outlookmentioning

confidence: 99%

A Survey of Techniques for Improving Security of Non-volatile Memories

Mittal

Alsalibi²

2018

J Hardw Syst Secur

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Due to their high-density and near-zero leakage power consumption, non-volatile memories (NVMs) are promising candidates for designing future memory systems. However, compared to conventional memories, NVMs also face more severe security threats, e.g., the limited write endurance of NVMs makes them vulnerable to write attacks. Also, the nonvolatility of NVMs allows the data to persist even after power-off, which can be accessed by a malicious agent. Further, encryption endangers NVM lifetime and performance by reducing the efficacy of redundant write avoidance techniques. In this paper, we present a survey of techniques for improving security of NVM-based memories by addressing the aforementioned challenges. We highlight the key ideas of the techniques along with their similarities and differences. This paper is expected to be useful for researchers and practitioners in the area of memory and system security.

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Section: Conclusion and Future Outlookmentioning

confidence: 99%

A Survey of Techniques for Improving Security of Non-volatile Memories

Mittal

Alsalibi²

2018

J Hardw Syst Secur

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“…With increasing core count, the cache and main memory capacity is on the rise [11], and due to this, the overhead of correction techniques, such as scrubbing, is also growing [12]. STT-RAM and PCM are used for cache and main memory where any additional latency leads to a large impact on system performance.…”

Section: Need For Improving Nvm Reliabilitymentioning

confidence: 99%

A Survey of Soft-Error Mitigation Techniques for Non-Volatile Memories

Mittal

2017

Computers

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Non-volatile memories (NVMs) offer superior density and energy characteristics compared to the conventional memories; however, NVMs suffer from severe reliability issues that can easily eclipse their energy efficiency advantages. In this paper, we survey architectural techniques for improving the soft-error reliability of NVMs, specifically PCM (phase change memory) and STT-RAM (spin transfer torque RAM). We focus on soft-errors, such as resistance drift and write disturbance, in PCM and read disturbance and write failures in STT-RAM. By classifying the research works based on key parameters, we highlight their similarities and distinctions. We hope that this survey will underline the crucial importance of addressing NVM reliability for ensuring their system integration and will be useful for researchers, computer architects and processor designers.

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“…Focusing on hardware engineering, Sparsh M. et al provided a comprehensive survey of reliability techniques for microarchitecture design (such as processor registers, cache and main memory, etc.) [152]. Thaha M. et al surveyed the fault detection algorithms in WSN and performed a qualitative comparison of the latest fault detection researches including centralized, distributed and hybrid algorithms and analyzed the shortcomings, advantages of those algorithms.…”

Section: The Traditional Dependability Means and Vandvmentioning

confidence: 99%

A Comprehensive Technological Survey on Dependable Self-Managing CPS: The Decade of Researches on Correctness and Dependability

Zhou¹,

Hou²,

Zhang³

et al. 2017

Preprint

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Though Cyber Physical Systems (CPS) become very popular in last the decade, dependability of CPS is still a critical issue and related survey is rare. We try to spell out the jigsaw of technologies and figure out the technical trends of dependable self-managing CPS. This survey first recalls the motivation and the similar concepts. By analyzing four generic architectures, we summarize the common characteristics and related assurance technologies, and propose a more generic environment-in-loop processing flow of CPS and a formal interaction flow between physical space and cyber space. Further, the similarity between correctness and dependability is formally analyzed and the new five research questions of dependable self-managing CPS are presented. Then we review the critical technologies and related correctness verification & validation (V&V) methods, the architectures for dependable self-managing CPS. Further, the detail dependability management and V&V technologies are surveyed, which covers the areas of running-time fault management methods and whole life cycle V&V technologies, maintenance and available tool sets. For holistic CPS development, Modeling techniques and MDE (model driven engineering) based V&V methods are analyzed in detail. Then we complete the jigsaw of technologies and figure out the missing part. Further, we propose the technical challenges and the further direction. To our best knowledge, this is the first comprehensive survey on dependable self-managing CPS development and evaluation.

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A Survey of Techniques for Modeling and Improving Reliability of Computing Systems

Cited by 71 publications

References 114 publications

A Survey of Techniques for Improving Security of Non-volatile Memories

A Survey of Techniques for Improving Security of Non-volatile Memories

A Survey of Soft-Error Mitigation Techniques for Non-Volatile Memories

A Comprehensive Technological Survey on Dependable Self-Managing CPS: The Decade of Researches on Correctness and Dependability

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