A Survey of Techniques for Cache Locking

Mittal, Sparsh

doi:10.1145/2858792

Cited by 22 publications

(12 citation statements)

References 41 publications

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“…In multicore architecture, there may be unexpected cache misses due to execution occurring in other cores. Cache partitioning includes hardware-assisted cache lockdown (cache locking) [4] and software-based cache coloring [3].…”

Section: Related Workmentioning

confidence: 99%

“…Cache lockdown [4] divides the cache into way units and allocates available cache area to each core (or process). Cache lockdown is categorized as static locking or dynamic locking [32][33][34].…”

Section: Related Workmentioning

confidence: 99%

“…To reduce interference from shared resources on multiple cores, methods for dividing shared resources, such as allocation of memory and input-output (I/O) to each core [3,4], or limiting the usage of hardware resources in each core [5,6], have been proposed. Further, resource-aware scheduling [7,8] has been studied to control the execution order of tasks and to prevent interference due to redundant shared resource access.…”

Section: Introductionmentioning

confidence: 99%

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Execution Model to Reduce the Interference of Shared Memory in ARINC 653 Compliant Multicore RTOS

et al. 2020

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Multicore architecture is applied to contemporary avionics systems to deal with complex tasks. However, multicore architectures can cause interference by contention because the cores share hardware resources. This interference reduces the predictable execution time of safety-critical systems, such as avionics systems. To reduce this interference, methods of separating hardware resources or limiting capacity by core have been proposed. Existing studies have modified kernels to control hardware resources. Additionally, an execution model has been proposed that can reduce interference by adjusting the execution order of tasks without software modification. Avionics systems require several rigorous software verification procedures. Therefore, modifying existing software can be costly and time-consuming. In this work, we propose a method to apply execution models proposed in existing studies without modifying commercial real-time operating systems. We implemented the time-division multiple access (TDMA) and acquisition execution restitution (AER) execution models with pseudo-partition and message queuing on VxWorks 653. Moreover, we propose a multi-TDMA model considering the characteristics of the target hardware. For the interference analysis, we measured the L1 and L2 cache misses and the number of main memory requests. We demonstrated that the interference caused by memory sharing was reduced by at least 60% in the execution model. In particular, multi-TDMA doubled utilization compared to TDMA and also reduced the execution time by 20% compared to the AER model.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Execution Model to Reduce the Interference of Shared Memory in ARINC 653 Compliant Multicore RTOS

et al. 2020

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“…For example, caches could be loaded every time a function is entered (as in [54]), or explicitly through statements in the source code (scratchpad memory). Cache locking [45] provides an alternative mechanism to reach the same effect (which, incidentally, can improve the WCET [16]), and potentially qualifies many more processors for our approach. With these cache requirements, timing effects due to caches can be annotated in the source code as part of our analysis, and do not have to be modeled on instruction granularity.…”

Section: Wcet-amenable Processorsmentioning

confidence: 99%

Scalable and precise estimation and debugging of the worst-case execution time for analysis-friendly processors: a comeback of model checking

Becker¹,

Metta²,

Venkatesh³

et al. 2018

Int J Softw Tools Technol Transfer

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Estimating the Worst-Case Execution Time (WCET) of an application is an essential task in the context of developing real-time or safety-critical software, but it is also a complex and error-prone process. Conventional approaches require at least some manual inputs from the user, such as loop bounds and infeasible path information, which are hard to obtain and can lead to unsafe results if they are incorrect. This is aggravated by the lack of a comprehensive explanation of the WCET estimate, i.e., a specific trace showing how WCET was reached. It is therefore hard to spot incorrect inputs and hard to improve the worst-case timing of the application. Meanwhile, modern processors have reached a complexity that refutes analysis and puts more and more burden on the practitioner. In this article we show how all of these issues can be significantly mitigated or even solved, if we use processors that are amenable to WCET analysis. We define and identify such processors, and then we propose an automated tool set which estimates a precise WCET without unsafe manual inputs, and also reconstructs a maximum-detail view of the WCET path that can be examined in a debugger environment. Our approach is based on Model Checking, which however is known to scale badly with growing application size. We address this issue by shifting the analysis to source code level, where source code transformations can be applied that retain the timing behavior, but reduce the complexity. Our experiments show that fast and precise estimates can be achieved with Model Checking, that its scalability can even exceed current approaches, and that new opportunities arise in the context of "timing debugging".

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“…To reduce the analysis time, many studies propose using fully-lockable caches [10], present in processors of most manufacturers, such as Motorola (ColdFire, PowerPC, MPC7451, MPC7400), MIPS32, ARM (904, 946E-S), Integrated Device Technology (79R4650, 79RC64574), Intel 960, etc. These caches, on a miss event, request the missed line to the next memory level, but on arrival they send it to a line buffer, without keeping any copy.…”

Section: Introductionmentioning

confidence: 99%

Reducing the WCET and analysis time of systems with simple lockable instruction caches

et al. 2020

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One of the key challenges in real-time systems is the analysis of the memory hierarchy. Many Worst-Case Execution Time (WCET) analysis methods supporting an instruction cache are based on iterative or convergence algorithms, which are rather slow. Our goal in this paper is to reduce the WCET analysis time on systems with a simple lockable instruction cache, focusing on the Lock-MS method. First, we propose an algorithm to obtain a structure-based representation of the Control Flow Graph (CFG). It organizes the whole WCET problem as nested subproblems, which takes advantage of common branch-and-bound algorithms of Integer Linear Programming (ILP) solvers. Second, we add support for multiple locking points per task, each one with specific cache contents, instead of a given locked content for the whole task execution. Locking points are set heuristically before outer loops. Such simple heuristics adds no complexity, and reduces the WCET by taking profit of the temporal reuse found in loops. Since loops can be processed as isolated regions, the optimal contents to lock into cache for each region can be obtained, and the WCET analysis time is further reduced. With these two improvements, our WCET analysis is around 10 times faster than other approaches. Also, our results show that the WCET is reduced, and the hit ratio achieved for the lockable instruction cache is similar to that of a real execution with an LRU instruction cache. Finally, we analyze the WCET sensitivity to compiler optimization, showing for each benchmark the right choices and pointing out that O0 is always the worst option.

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A Survey of Techniques for Cache Locking

Cited by 22 publications

References 41 publications

Execution Model to Reduce the Interference of Shared Memory in ARINC 653 Compliant Multicore RTOS

Execution Model to Reduce the Interference of Shared Memory in ARINC 653 Compliant Multicore RTOS

Scalable and precise estimation and debugging of the worst-case execution time for analysis-friendly processors: a comeback of model checking

Reducing the WCET and analysis time of systems with simple lockable instruction caches

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