A Survey on Cache Management Mechanisms for Real-Time Embedded Systems

Gracioli, Giovani; Alhammad, Ahmed; Mancuso, Renato; Fröhlich, Antônio Augusto; Pellizzoni, Rodolfo

doi:10.1145/2830555

Cited by 86 publications

(43 citation statements)

References 98 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Software approaches to perform partitioning have also been studied in the literature. These are usually implemented at compiler-level [29], [30], [6], with changes to the application [5], [32], or at the OS level [20], [47], [8], [44], [23]. These solutions limit the portability for cache partitioning mechanisms, because they require modifications to the toolchain, the OS, or both.…”

Section: Related Workmentioning

confidence: 99%

Deterministic Memory Hierarchy and Virtualization for Modern Multi-Core Embedded Systems

Kloda

Solieri

Mancuso

et al. 2019

2019 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)

Self Cite

View full text Add to dashboard Cite

One of the main predictability bottlenecks of modern multi-core embedded systems is contention for access to shared memory resources. Partitioning and software-driven allocation of memory resources is an effective strategy to mitigate contention in the memory hierarchy. Unfortunately, however, many of the strategies adopted so far can have unforeseen side-effects when practically implemented latest-generation, highperformance embedded platforms. Predictability is further jeopardized by cache eviction policies based on random replacement, targeting average performance instead of timing determinism. In this paper, we present a framework of software-based techniques to restore memory access determinism in highperformance embedded systems. Our approach leverages OStransparent and DMA-friendly cache coloring, in combination with an invalidation-driven allocation (IDA) technique. The proposed method allows protecting important cache blocks from (i) external eviction by tasks concurrently executing on different cores, and (ii) internal eviction by tasks running on the same core. A working implementation obtained by extending the Jailhouse partitioning hypervisor is presented and evaluated with a combination of synthetic and real benchmarks.

show abstract

Section: Related Workmentioning

confidence: 99%

Deterministic Memory Hierarchy and Virtualization for Modern Multi-Core Embedded Systems

Kloda

Solieri

Mancuso

et al. 2019

2019 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)

Self Cite

View full text Add to dashboard Cite

show abstract

“…A thorough survey on cache designs and time predictability can be found in [117]. Details on the pros and cons of cache memories for probabilistic timing analysis is further developed by Cazorla et al [64].…”

Section: Cachementioning

confidence: 99%

Multi-core Devices for Safety-critical Systems

et al. 2020

View full text Add to dashboard Cite

Multi-core devices are envisioned to support the development of next-generation safety-critical systems, enabling the on-chip integration of functions of different criticality. This integration provides multiple system-level potential benefits such as cost, size, power, and weight reduction. However, safety certification becomes a challenge and several fundamental safety technical requirements must be addressed, such as temporal and spatial independence, reliability, and diagnostic coverage. This survey provides a categorization and overview at different device abstraction levels (nanoscale, component, and device) of selected key research contributions that support the compliance with these fundamental safety requirements.

show abstract

“…However, dynamic locking can reduce the determinism of real-time systems, such as avionics systems, because it modifies cache locking information at run time [35]. Moreover, there is data or instruction cache locking [33,36] as well as user space or kernel space locking [37]. These cache lockdown methods depend on variables, such as the number of cache lockdown entries supported by the hardware.…”

Section: Related Workmentioning

confidence: 99%

Execution Model to Reduce the Interference of Shared Memory in ARINC 653 Compliant Multicore RTOS

et al. 2020

View full text Add to dashboard Cite

Multicore architecture is applied to contemporary avionics systems to deal with complex tasks. However, multicore architectures can cause interference by contention because the cores share hardware resources. This interference reduces the predictable execution time of safety-critical systems, such as avionics systems. To reduce this interference, methods of separating hardware resources or limiting capacity by core have been proposed. Existing studies have modified kernels to control hardware resources. Additionally, an execution model has been proposed that can reduce interference by adjusting the execution order of tasks without software modification. Avionics systems require several rigorous software verification procedures. Therefore, modifying existing software can be costly and time-consuming. In this work, we propose a method to apply execution models proposed in existing studies without modifying commercial real-time operating systems. We implemented the time-division multiple access (TDMA) and acquisition execution restitution (AER) execution models with pseudo-partition and message queuing on VxWorks 653. Moreover, we propose a multi-TDMA model considering the characteristics of the target hardware. For the interference analysis, we measured the L1 and L2 cache misses and the number of main memory requests. We demonstrated that the interference caused by memory sharing was reduced by at least 60% in the execution model. In particular, multi-TDMA doubled utilization compared to TDMA and also reduced the execution time by 20% compared to the AER model.

show abstract

A Survey on Cache Management Mechanisms for Real-Time Embedded Systems

Cited by 86 publications

References 98 publications

Deterministic Memory Hierarchy and Virtualization for Modern Multi-Core Embedded Systems

Deterministic Memory Hierarchy and Virtualization for Modern Multi-Core Embedded Systems

Multi-core Devices for Safety-critical Systems

Execution Model to Reduce the Interference of Shared Memory in ARINC 653 Compliant Multicore RTOS

Contact Info

Product

Resources

About