The use of multicore CPUs in real-time systems poses significant challenges in estimating their temporal behavior. A factor that has a large impact on this issue is the contention for access to main memory among multiple cores. To overcome this problem, an execution model called PREM has been previously introduced to co-schedule CPU execution and accesses to main memory without relying on hardware arbiters. In this paper, we provide a global schedulability analysis for this predictable execution model, and we prove its correctness. We also evaluate the effectiveness of the proposed solution with extensive simulations. The results show a significant advantage of the proposed solution when compared to contention execution in which tasks access main memory unpredictably.

Multicore processors are being extensively used by real-time systems, mainly because of their demand for increased computing power. However, multicore processors have shared resources that affect the predictability of real-time systems, which is the key to correctly estimate the worst-case execution time of tasks. One of the main factors for unpredictability in a multicore processor is the cache memory hierarchy. Recently, many research works have proposed different techniques to deal with caches in multicore processors in the context of real-time systems. Nevertheless, a review and categorization of these techniques is still an open topic and would be very useful for the real-time community. In this article, we present a survey of cache management techniques for real-time embedded systems, from the first studies of the field in 1990 up to the latest research published in 2014. We categorize the main research works and provide a detailed comparison in terms of similarities and differences. We also identify key challenges and discuss future research directions.

Current computing architectures are commonly built with multiple cores and a single shared main memory. Even though this architecture increases the overall computation power, main memory can easily become a bottleneck. Simultaneous access to main memory from multiple cores can cause both (1) severe degradation in performance and (2) unpredictable execution time for real-time applications. We propose in this paper to mitigate these two problems by co-scheduling cores as well as the main memory for predictable execution. In particular, we use a DMA component to overlap memory with computation for hiding the memory latency and therefore increasing the system performance. The main contribution of this paper is a novel global co-scheduling algorithm along with its associated schedulability analysis for sporadic hard real-time tasks. We evaluated our system by generating synthetic tasksets based on real benchmark parameters. The results show a significant improvement in system utilization while retaining a predictable system behavior.

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