Time-predictable execution of multithreaded applications on multicore systems

Alhammad, Ahmed; Pellizzoni, Rodolfo

doi:10.7873/date.2014.042

Cited by 17 publications

(24 citation statements)

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“…We adopt the read-execute-write semantics found in the papers [3], [4], [5], and an extension of the PREM (Predictable Execution Model) [10], [11], to accurately estimate contentions. Each task (node) of a DAG is divided into three phases: read, execute, and write.…”

Section: Read-execute-write Semanticsmentioning

confidence: 99%

Accurate Contention-aware Scheduling Method on Clustered Many-core Platform

Igarashi

Fukunaga

Azumi

2021

Journal of Information Processing

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Embedded systems such as self-driving systems require a computing platform with high computing power and low power consumption. Multi-/many-core platforms definitely meet these requirements. However, for hard realtime applications, multiple demands on shared resources can hinder real-time performance. Memory is one of the resources that can most dramatically impair desired performance. Therefore, we addressed contentions induced by shared memory. The ability to predict contentions that may occur during memory access helps to reduce them. We improved the predictability of contentions by dividing tasks into the memory access phase and the execution phase using a Directed Acyclic Graph (DAG). Existing methods can make accurate contention estimations for one Compute Cluster (CC) of a clustered many-core processor. Our method is able to perform accurate contention estimations for multiple CCs, thereby doubling the scalability when contentions are taken into account. Using an Integer Linear Programming (ILP) formulation, we produced a static, non-preemptive, partitioned, and time-triggered schedule. We also conducted an experiment in order to minimize the makespan. The evaluation confirmed that our new method reduced the makespan by increasing the number of CCs.

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Section: Read-execute-write Semanticsmentioning

confidence: 99%

Accurate Contention-aware Scheduling Method on Clustered Many-core Platform

Igarashi

Fukunaga

Azumi

2021

Journal of Information Processing

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“…The research on precision time architectures concerns global aspects of the problem and tries to formulate general principles like [1, 5, 12–15]. Other investigations are carried out towards finding the detailed solution in the selected software [16–19] or hardware [4, 5, 15, 20–22] aspects. MA operations that are responsible for a generation of the greatest amount of ‘unpredictability’ are addressed in many works [1, 3, 7, 8, 16, 20, 23].…”

Section: Related Workmentioning

confidence: 99%

Flexible hardware approach to multi‐core time‐predictable systems design based on the interleaved pipeline processing

Antolak

Pułka

2020

IET Circuits, Devices & Systems

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The study presents a hardware-based approach to modelling and design of time-predictable electronic embedded systems. It addresses multithread and multitask problems of contemporary real-time systems. Authors propose a universal template of the reconfigurable system architectures that can be flexibly accommodated to a given application. The synthesisable and parametrised model of the system architecture has been implemented in VERILOG. The architecture is based on ARM-like RISC solutions and its heart, the main core, is built of 8-12 stage reconfigurable pipelining with the interleaving mechanism. This core is a basic building block of the system and it can be replicated. Each core can handle several hardware threads with replicated register files. The entire structure has a deadline controlling mechanism that is responsible for tasks' evaluation predictability. The authors analyse the coherency of the proposed memory system and interoperability between hardware threads. Three different static scheduling algorithms have been developed and presented in examples. This study contains the results of the simulation experiments and the summary of the hardware implementation in Virtex-7 FPGA platforms. Authors have investigated the timing parameters of the system and pointed out the areas for further research.

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“…The approach has been refined in successive works [6,66] into three phases. Specifically, two memory phases are considered: an acquisition (or load) phase that copies data and instructions from main memory into local memory, and a replication (or unload) phase that copies modified data back to main memory.…”

Section: Software Solutionsmentioning

confidence: 99%

“…Specifically, two memory phases are considered: an acquisition (or load) phase that copies data and instructions from main memory into local memory, and a replication (or unload) phase that copies modified data back to main memory. While the computation phase is always executed on a processor, the memory phases can be either executed on the processor itself [5,6,13,22,26,49,50,53,56,71,72], or on another hardware component [30,31], such as a programmable Direct Memory Access (DMA) module [7,20,61,66]. Works that proposed using a DMA unit to perform the memory transfers [66] can efficiently hide the memory latency by overlapping the execution of a task with the DMA transfer of another task; this leads to considerable improvements in schedulability.…”

Section: Software Solutionsmentioning

confidence: 99%