Flexible hardware approach to multi‐core time‐predictable systems design based on the interleaved pipeline processing

Abstract

The study presents a hardware-based approach to modelling and design of time-predictable electronic embedded systems. It addresses multithread and multitask problems of contemporary real-time systems. Authors propose a universal template of the reconfigurable system architectures that can be flexibly accommodated to a given application. The synthesisable and parametrised model of the system architecture has been implemented in VERILOG. The architecture is based on ARM-like RISC solutions and its heart, the main core, is built of 8-12 stage reconfigurable pipelining with the interleaving mechanism. This core is a basic building block of the system and it can be replicated. Each core can handle several hardware threads with replicated register files. The entire structure has a deadline controlling mechanism that is responsible for tasks' evaluation predictability. The authors analyse the coherency of the proposed memory system and interoperability between hardware threads. Three different static scheduling algorithms have been developed and presented in examples. This study contains the results of the simulation experiments and the summary of the hardware implementation in Virtex-7 FPGA platforms. Authors have investigated the timing parameters of the system and pointed out the areas for further research.

Validation of Task Scheduling Techniques in Multithread Time Predictable Systems

“…In the paper [1], an original real-time system solution was proposed. It was based on thread interleaved pipeline processing.…”

“…In that case, there is no need for complex forwarding and jump prediction circuits. The thread interleaving method has been extended by the authors [1], [2] and has also been used to exchange data between tasks. The proposed architecture is based on pipeline processing.…”

“…The microarchitecture of our system is modeled after the ISA (Instruction Set Architecture) of the ARM processor family. ISA was enhanced with special timing instructions [1]:…”

“…The procedure of launching a given thread can be implemented either hardware-wise (using an external interrupt) or software-wise by executing the corresponding instruction by another processor thread. The system architecture is based on the authors' previous solutions [1], [2], [29]. The current implementation of the system allows simultaneous processing of up to 255 different tasks, with theoretically any distribution of these tasks between cores (the theoretical maximum number of cores is also 255).…”

Embedded Microprocessor Extension Design and Optimization for Real-Time Edge Computing

“…Liu reduced the first five of the six instructions into four instructions in his dissertation [42] and implemented them in PTARM processor. Antolak and Pulka [43] extended the instruction set and added four timing instructions to a multicore timing predictable processor. Broman et al [44] introduced their extension of temporal semantics based on llvm.…”