Memory efficient global scheduling of real-time tasks

Alhammad, Ahmed; Wasly, Saud; Pellizzoni, Rodolfo

doi:10.1109/rtas.2015.7108452

Cited by 40 publications

(35 citation statements)

References 37 publications

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“…In this section the approach presented in this paper is compared against the approach presented in [2], [11] using randomly synthetically generated task sets 4 . The generation parameters are detailed next.…”

Section: Resultsmentioning

confidence: 99%

“…In Fig. 7, the green line ('OUR') presents the results for the approach presented in this paper and the red line ('ALHM') presents the results for [2], [11].…”

Section: Resultsmentioning

confidence: 99%

“…The only works, to the best of our knowledge, that follow the same line of research as the work presented in this paper are the works presented by Alhammad and Pellizzoni in [2] and in Chapter 3 of [11]. Alhammad's work focuses on the schedulability analysis of the 3-phase task model by upper-bounding the interference a task suffers in a problem window from a core's perspective.…”

Section: Related Workmentioning

confidence: 93%

“…Finally, one should note that the method presented in this paper does not dominate the analysis in [2], [11]. There exist task sets that are deemed unschedulable by our method but which are deemed schedulable by 'ALHM', as depicted in Fig.…”

Section: MImentioning

confidence: 94%

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Schedulability analysis for global fixed-priority scheduling of the 3-phase task model

Maia

Nelissen

Nogueira

et al. 2017

2017 IEEE 23rd International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)

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Scheduling real-time applications on general purpose multicore platforms is a challenging problem from atiming analysis perspective. Such platforms expose uncontrolledsources of interference whenever concurrent accesses to memoryare performed. The non-deterministic bus and memory accessbehavior complicates the estimations of applications 19 worst-caseexecution times (WCET).The 3-phase task model seems a good candidate to circumventthe uncontrolled sources of interference by isolating concurrentmemory accesses. A task is divided in three successive phases;first, the task loads its instruction and data in a local memory,then it executes nonpreemptively using those pre-loaded instructions and data, and finally, the modified data are pushed back tomain memory. Following this execution model, tasks never accessthe bus during their execution phase. Instead, all the bus accessesare performed during the first and third phases.In this paper, we focus on the global fixed-priority schedulingof the 3-phase task model. A new schedulability test is derivedby modelling the interference happening on the bus rather thanthe interference on the cores as in the state-ot-the-art techniques.The effectiveness of the test is evaluated by comparing it againstthe state-of-the-art. Abstract-Scheduling real-time applications on general purpose multicore platforms is a challenging problem from a timing analysis perspective. Such platforms expose uncontrolled sources of interference whenever concurrent accesses to memory are performed. The non-deterministic bus and memory access behavior complicates the estimations of applications' worst-case execution times (WCET).The 3-phase task model seems a good candidate to circumvent the uncontrolled sources of interference by isolating concurrent memory accesses. A task is divided in three successive phases; first, the task loads its instruction and data in a local memory, then it executes non-preemptively using those pre-loaded instructions and data, and finally, the modified data are pushed back to main memory. Following this execution model, tasks never access the bus during their execution phase. Instead, all the bus accesses are performed during the first and third phases.In this paper, we focus on the global fixed-priority scheduling of the 3-phase task model. A new schedulability test is derived by modelling the interference happening on the bus rather than the interference on the cores as in the state-ot-the-art techniques. The effectiveness of the test is evaluated by comparing it against the state-of-the-art.

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Section: Resultsmentioning

confidence: 99%

“…In Fig. 7, the green line ('OUR') presents the results for the approach presented in this paper and the red line ('ALHM') presents the results for [2], [11].…”

Section: Resultsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 93%

Section: MImentioning

confidence: 94%

See 2 more Smart Citations

Schedulability analysis for global fixed-priority scheduling of the 3-phase task model

Maia

Nelissen

Nogueira

et al. 2017

2017 IEEE 23rd International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)

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“…Lampka et al (2014) proposed a formal approach for bounding the worst-case response time of concurrently executing real-time tasks under resource contention and almost arbitrarily complex resource arbitration policies, with a focus on main memory as a shared resource. Global scheduling of PREM tasks has also been considered by Alhammad and Pellizzoni (2014) and Alhammad et al (2015).…”

Section: Related Work Assuming Different Application Modelsmentioning

confidence: 99%

An extensible framework for multicore response time analysis

et al. 2017

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In this paper, we introduce a multicore response time analysis (MRTA) framework, which decouples response time analysis from a reliance on contextindependent WCET values. Instead, the analysis formulates response times directly The additional material includes: Section 4: analysis for warmed-up caches and dynamic scratchpads (Sects. 4.3 and 4.2). Section 7: extensions to the task model, including RTOS and interrupts, shared software resources, and open systems and incremental verification. Section 8: presentation of a cycle-accurate multicore simulator. Section 9: evaluation of different local memory types (Sect. 9.2), a comparison between predictable and reference architectures (Sect. 9.3), and a verification of the precision of the analysis using results from the simulator (Sect. 9.4). 123Real-Time Syst from the demands placed on different hardware resources. The MRTA framework is extensible to different multicore architectures, with a variety of arbitration policies for the common interconnects, and different types and arrangements of local memory. We instantiate the framework for single level local data and instruction memories (cache or scratchpads), for a variety of memory bus arbitration policies, including: Round-Robin, FIFO, Fixed-Priority, Processor-Priority, and TDMA, and account for DRAM refreshes. The MRTA framework provides a general approach to timing verification for multicore systems that is parametric in the hardware configuration and so can be used at the architectural design stage to compare the guaranteed levels of real-time performance that can be obtained with different hardware configurations. We use the framework in this way to evaluate the performance of multicore systems with a variety of different architectural components and policies. These results are then used to compose a predictable architecture, which is compared against a reference architecture designed for good average-case behaviour. This comparison shows that the predictable architecture has substantially better guaranteed real-time performance, with the precision of the analysis verified using cycle-accurate simulation.

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Analysemethodiken zur Berechnung der WCET mit asynchroner Ein-/Ausgabeverarbeitung

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2022

Informatik Aktuell

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Memory efficient global scheduling of real-time tasks

Cited by 40 publications

References 37 publications

Schedulability analysis for global fixed-priority scheduling of the 3-phase task model

Schedulability analysis for global fixed-priority scheduling of the 3-phase task model

An extensible framework for multicore response time analysis

Analysemethodiken zur Berechnung der WCET mit asynchroner Ein-/Ausgabeverarbeitung

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