A switch level fault simulation environment

Krishnaswamy, V.; Casas, Jérôme; Tetzlaff, Thomas

doi:10.1145/337292.337777

Cited by 16 publications

(4 citation statements)

References 7 publications

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“…SLS has been wildly used to evaluate the CMOS logic which treats each transistor as ON/OFF switching path. One of SLS applications is switching path modeling treated as stuck-at fault [3,4]. Voltage rather than stuck-at fault value is, however, beneficial data for precise fault diagnosis, and hence a novel way combined SLS with voltage analysis on transistor level have been developed.…”

Section: Diagnosis Conceptmentioning

confidence: 99%

Voltage-based fault path tracing by transistor operating point analysis

Sanada

2008

Microelectronics Reliability

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A novel diagnosis method has been developed based on transistor operating point analysis. The method is worked by the way of fault logic propagation trace based on voltage value and the way of operation time setting of each gate circuit. The former way is to detect penetration current net result from fault, replace the net with impedance net, calculate voltage value of each node of the impedance net by OHM's low, and then sequentially trace the fault logic propagation. The latter way is to set a standardized operation time at each gate circuit, and then, the virtual terminal is prepared at output point of gate unit. The proposed method makes it possible to detect not only signal propagation of each gate in order of time, but oscillation phenomenon brought by feedback fault.

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Section: Diagnosis Conceptmentioning

confidence: 99%

Voltage-based fault path tracing by transistor operating point analysis

Sanada

2008

Microelectronics Reliability

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“…Krishnaswamy et al presented a ternary, switch-level simulator with fault simulation capabilities [19]. The simulator extracts a circuit model similar to the COSMOS system.…”

Section: P Krishnaswamy Et Almentioning

confidence: 99%

A survey and comparison of digital logic simulators

Güneş¹,

Thornton²,

Kocan³

et al. 2005

48th Midwest Symposium on Circuits and Systems, 2005.

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In this paper, we present a comprehensive survey of digital logic simulators from the past twenty years to present. First, we summarize the digital logic simulation characteristics. Next, we analyze a comprehensive set of simulators for their timing model, simulation mode, logic values, and fault simulation capabilities. I. LOGIC SIMULATION CHARACTERISTICSSeveral fundamental issues describe the functionality and flexibility of a digital logic circuit simulator. Primary among these considerations is the implementation of the basic simulation mechanism. There are two basic methods for digital logic simulation, compiled and event-driven simulations [23]. A. Compiled simulationA compiled simulator converts the circuit netlist into a sequence of machine language instructions that reflect the functions and interconnections of every element in the circuit. A circuit value table contains an entry that stores the current value of each logic element or net. The instructions obtain input values from this table and store results back into the table. Output values are computed using machine language instructions that reflect the function of the element. Compiled simulation is mainly oriented toward functional verification particularly since it is not concerned with the timing of the circuit. Since compiled simulators do not provide the accurate timing estimates, we will focus on event-driven simulators in the remainder of this paper. B. Event-driven simulationAn event-driven simulator can be implemented to operate on a set of tables that model the circuit. For each circuit node (net), the table has an entry of the logic state and the strength of the source or sources driving the node. An event is said to have occurred when a signal changes state on an input or the output of a circuit element, and is stored in an event queue to be scheduled. The simulator keeps track of the current time and the event queue that holds future events. An evaluation list keeps track of circuit elements whose inputs have changed. The evaluation list is processed after the event queue is processed for that time point. This chain of eventqueue processing followed by the evaluation-list processing is a simulation cycle.One efficient method to increase simulator performance is that of selective trace which greatly reduces the number of events to be triggered. It is based on the fact that some of the events may not alter the output of an element, so fan-out of this element is unaltered by the excitation that caused the evaluation. Thus, when an element's output does not change after computing with updated inputs, following its fan-out is unnecessary. C.Timing model The circuits being modeled rely both on correct logical operation of the components in the circuit and on correct relative timing of signals passing through the circuit. In an event-driven simulation, wires are usually assumed to be without any delay and logic elements are typically assumed to have lumped delay. The timing model of a simulator can vary from zero delay to min/max delay. A zero...

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“…The switch-level is an abstraction-level, which is more accurate and detailed than gate-level models [13] and can be used in many applications such as design verification [5][10] and fault simulation [11]. However, the simulation of switch-level models is more time-consuming than gate-level models.…”

Section: Introductionmentioning

confidence: 99%

Switch-level emulation

Ejlali

Miremadi

2003

Proceedings of the 40th Annual Design Automation Conference

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This paper presents a method for the fast emulation of switchlevel circuits using FPGAs. In this method, logic gates are used to model switch-level circuits without any abstraction. In contrast to the abstraction methods for which transistors are grouped together to form gates, in this method, gates are grouped together to form the switch models of transistors. Unlike the abstraction methods, the method presented in this paper can emulate many important features of switch-level models, such as bi-directional signal propagation and variations in driving strength. In order to attain a better utilization of FPGA resources a mixed-mode emulation approach has been used. In this approach parts of the circuit are emulated at the switch-level while the rest of the circuit is emulated at the gate-level.

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A switch level fault simulation environment

Cited by 16 publications

References 7 publications

Voltage-based fault path tracing by transistor operating point analysis

Voltage-based fault path tracing by transistor operating point analysis

A survey and comparison of digital logic simulators

Switch-level emulation

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