A symbol based algorithm for hardware implementation of cyclic redundancy check (CRC)

Nair, Remya.R.; Ryan, G.; Farzaneh, F.

doi:10.1109/viuf.1997.623934

Cited by 16 publications

(7 citation statements)

References 3 publications

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“…The (23, 12) Golay code is a multiple error correcting binary code capable of correcting an combination of three or few random errors in a block of 23 digits. For hardware implementation of encoding process, Linear Feedback Shift Register (LFSR) based cyclic redundancy check (CRC) generation method is preferred conventionally [11]. Due to drawbacks like high latency and less throughput, this technique is not a suitable solution for high-speed applications.…”

Section: Fig 5 Bwa Architecture For Systematic Code Wordsmentioning

confidence: 99%

VLSI Design of a Novel Architecture for Data Encoding with Golay codes

Odevi¹

2018

IJRASET

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There is an expanding interest for productive and dependable transmission of computerized information. A noteworthy worry here is the control of blunders for dependable generation of information. By appropriate encoding of data to a codeword with the assistance of Error Correction Codes (ECC), errors induced can be reduced. The proposed architecture parallelizes the comparison of the data and that of the parity information. To further reduce the latency and complexity, in addition, a new butterfly-formed weight accumulator (BWA) is proposed for the proficient calculation of the Hamming separation. Grounded on the BWA, the proposed design analyzes whether the approaching information coordinates the put away information if a specific number of wrong bits are amended. . The proposed engineering is actualized by utilizing xilinx14.7 form and the trial comes about demonstrate that the proposed design lessens the dormancy and the equipment multifaceted nature separately. In expansion we do Golay code for more decrease in the idleness. Golay code is a different mistake adjusting parallel code equipped for remedying a blend of three or couple of arbitrary blunders in a piece of 23 digits. The Comparison of Golay Code and BWA is due to Delay and Speed.

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Section: Fig 5 Bwa Architecture For Systematic Code Wordsmentioning

confidence: 99%

VLSI Design of a Novel Architecture for Data Encoding with Golay codes

Odevi¹

2018

IJRASET

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“…Since configuration bitstreams are updated with the HW task state information, the CRC value contained in the bitstream is no more valid and requires recalculation. We implemented the parallel CRC algorithm [14] in hardware. It allows for onthe-fly calculation of the bitstream's CRC value and automatic replacement of the old value, without incurring any delays.…”

Section: Reconfiguration/readback Controllermentioning

confidence: 99%

A Novel Framework for Effective Preemptive Hardware Multitasking on FPGAs

Jozwik

Tomiyama

Honda

et al. 2012

IEICE Trans. Inf. & Syst.

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SUMMARYModern FPGAs (Field Programmable Gate Arrays), such as Xilinx Virtex-4, have the capability of changing their contents dynamically and partially, allowing implementation of such concepts as a HW (hardware) task. Similarly to its software counterpart, the HW task shares time-multiplexed resources with other HW tasks. To support preemptive multitasking in such systems, additional context saving and restoring mechanisms must be built practically from scratch. This paper presents an efficient method for hardware task preemption which is suitable for tasks containing both Flip-Flops and memory elements. Our solution consists of an offline tool for analyzing and manipulating bitstreams, used at the design time, as well as an embedded system framework. The framework contains a DMA-based (Direct Memory Access), instruction-driven reconfiguration/readback controller and a developed lightweight bus facilitating management of HW tasks. The whole system has been implemented on top of the Xilinx Virtex-4 FPGA and showed promising results for a variety of HW tasks.

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“…A ripple implementation of XOR tree will lead to very low timing path. We employ a balanced multi-level XOR tree to obtain better timing, which is detailed in [5].…”

Section: Fig 5 Frame Formatmentioning

confidence: 99%

Design of dual-gigabit transceiver for fibre channel FC-1 layer

Sun

2008

2008 IEEE International Conference on Electron Devices and Solid-State Circuits

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Fibre channel is a gigabit-speed network technology which dominates today's high-end storage network market. Its topology consists of several layers. This paper presents a transceiver design with FS-HSPI compliant interface used for Fibre Channel Transmission Protocol Layer or FC-1 layer. Optimized 8B/10B encoder/decoder architecture and parallel CRC checking algorithm are used in order to satisfy high-speed requirements and ensure reliability during transmission. By providing DDR/SDR interface, the transceiver can support both 1.0625Gbit/s and 2.125Gbit/s transmission rate. FIFO buffering and clock correction technique are used to accommodate the rate difference between recovered clock and receiver clock. Synthesis results using Synopsys Design Compiler in SMIC 0.18um technology shows our design can reach the required baud rate.

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A symbol based algorithm for hardware implementation of cyclic redundancy check (CRC)

Cited by 16 publications

References 3 publications

VLSI Design of a Novel Architecture for Data Encoding with Golay codes

VLSI Design of a Novel Architecture for Data Encoding with Golay codes

A Novel Framework for Effective Preemptive Hardware Multitasking on FPGAs

Design of dual-gigabit transceiver for fibre channel FC-1 layer

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