A synthesizable AXI protocol checker for SoC integration

Chen, Chien‐Hung; Ju, Jiun-Cheng; Huang, Ing-Jer

doi:10.1109/socdc.2010.5682961

Cited by 14 publications

(5 citation statements)

References 14 publications

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“…The V. CONCLUSION Therefore, the AMBA AXI protocol was checked using System Verilog and got simulation results has been seen in fig (9,10,11). This main idea is to see the read and write operation happening.…”

Section: Resultsmentioning

confidence: 99%

Testing of AMBA AXI Protocol

Tanupriya¹,

Kiran²

2022

Int J Res Rev

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The rapidly expanding VLSI sector has a great need for a very robust verification mechanism that can be developed in a short amount of time in the constantly changing environment where new intellectual property and chips are being designed every day having reduced time-to-market. (SoC) System on Chip design emerged as a primary integrated technique for reducing the design time of the entire system with the introduction of a standardized signal bus architecture used for the connectivity of different modules of the system. One of the major difficulties at hand is how to check these on chip bus protocols, since traditional old methods are ineffective in certifying large SoCs. In this paper, we have verified AMBA AXI protocol which shows write as well as read operations using System Verilog. Keywords: AMBA AXI, APB, AHB.

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Section: Resultsmentioning

confidence: 99%

Testing of AMBA AXI Protocol

Tanupriya¹,

Kiran²

2022

Int J Res Rev

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“…The locked and exclusive transfer is also not verified. Chen et al [21] in order to combat the growing complexity of increasing bus transactions propose a rule-based verification methodology in which they try to encapsulate the 44 rules to establish onchip accuracy. The benefits of using rule-based design include improving observability, reducing debug time, improving integration through correct usage checking, and improving communication through documentation.…”

Section: Literature Surveymentioning

confidence: 99%

Deployment of Formal Verification Methodology for AXI based Protocol for a Memory Model Verification

Awasthi

2023

SKITRJ

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AXI Protocol is an On-Chip Communication Protocol used for communication between different Intellectual Property blocks inside a System-On-Chip. With increasing logic density and a plethora of blocks interacting with each other, it becomes pertinent to not only verify the functional correctness of individual IP's but also to evaluate the integrity of transactions amongst each other. Simulation-based techniques fail to exhaustively assess all the kinds of transactions possible and primarily focus only on a few critical areas for AXI Protocol Verification. This paper proposes the integration of SystemVerilog Assertions coupled with Coverage model to verify the AXI Transactions from Master to Slave. This would aid in developing Verification Intellectual Property (VIP) helping in developing modular reusable components which can be leveraged across different verifications cycles. This paper demonstrates it empirically harvesting results relevant to building Assertion based verification, calculation of bus utilization factor and Coverage closure for RTL Signoff.

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“…They have concentrated on read and write operations with no information loss in this work. The authors [9] have used a reusable in-constructed verification referred to as Verification IP [Intellectual property] Cores for discount of time in verification and simulation using device Verilog and Mentor graphics Questasim. They have taken 5 form of test instances and have checked the useful verification and the overall performance was calculated based on valid count number, busy remember and bus utilization thing.…”

Section: B Based On Verificationmentioning

confidence: 99%

A Review on Design Implementation and Verification of AMBA AXI- 4 lite Protocol for SoC Integration

Hemanthraju¹

2022

IJRASET

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The present modern bus protocols used for communication between different functional blocks on a System-on-Chip (Soc) designs face many different challenges among which complexity and communication management are the most important factors. These on-chip communications directly impact performance and functionality, hence depending on the application where the bus protocol is to be used, a perfect communication protocol is chosen. AMBA (Advanced Microcontroller Bus Architecture) provides various types of protocols to be used as IP, of which AXI4 (Advance Extensible Interface), is one of the widely used protocols for SoC designs. Out of its three different interconnect protocols: lite, stream and burst, AXI4-lite has the simplest architecture design that best suits to be used in applications where power, area and performance play a vital role. This paper briefs about using AMBA AXI4-lite bus protocol with more bus efficiency and performance in an SoC design for proper communication between various functional blocks present. The RTL is verified using UVM (Universal Verification Methodology) and various designing process is carried out using cadence tools.

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A synthesizable AXI protocol checker for SoC integration

Cited by 14 publications

References 14 publications

Testing of AMBA AXI Protocol

Testing of AMBA AXI Protocol

Deployment of Formal Verification Methodology for AXI based Protocol for a Memory Model Verification

A Review on Design Implementation and Verification of AMBA AXI- 4 lite Protocol for SoC Integration

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