A Synthesizable Memory Grid using BRAMs and Function Generators to Enhance Throughput Efficiency in Regular Expression Pattern Matching Circuits

Abstract

Attacks on various computer networks are usually in form of patterns of attack. The patterns are recognizable mostly based on the data that the respective packet payloads contain. Attack patterns usually occur as strings or regular expression patterns, which are then converted into their equivalent automata. To create an efficient automata, there is a need for the automata design to consume less memory resources per each state of the automata. This is important whenever the design attempts to detect variations of these patterns. This paper explains the design, structure, and suitability of the hardware memory architecture for a Field Programmable Gate Array (FPGA) based automata design. The new design implementation is based on the input compression technique called Equivalence Classification (EC) which is used to drive a Nondeterministic Fine Automata (NFA) referred to as Equivalence Class Decoding NFA (ECD-NFA). The ECD-NFA approach creates classes of compressed inputs represented by positive integers simply called ECDs, which are the class descriptors. The compressed ECDs are then used to drive the automata, instead of unclassified raw character-inputs. This paper further extends the design by creating a memory grid that utilizes half the total number of required primitive block RAMs (BRAMS). Also, by rewriting the algorithm for the table look-up operation, the design utilizes a minimal number of function generators. Function generators are implemented as 6-input look-up tables (LUTs) on the target Xilinx FPGA Virtex-6 device. The efficiency of such LUT-based designs is determined by the throughput efficiency. The throughput efficiency (TE) is computed based on the ratio of LUTs utilized by the states of the automata and the design throughput. The preliminary results obtained for the TE is 3.55, while the clock rate obtained was 440.51MHz