Network attacks that flow through network firewalls or network intrusion detection systems (NIDS

Due to the importance of forecasting the capital market earnings in finance, recently the aspect of stock market prediction has been a major research area that has generated a lot of attention involving various machine learning algorithms. In the recent presentations, it has been indicated that neural networks have some drawbacks in learning the data patterns or that they may perform inconsistently and unpredictable because of the complexity of the stock market data. However, due to the distributive nature of the capital market, a computational intelligence technique called Ant Colony Optimization (ACO) which is suitable for solving distributed control problem was applied in this paper, to get the most optimal solution from three technical analysis strategies. The obtained optimal prediction of the next day closing stock price the ACO algorithm performs better than the other three approaches (Price Momentum Oscillator, Stochastic and Moving Average). Our algorithm (ACO based) was evaluated to have the accuracy of 0.812500, Sensitivity of 0.907407 and Specificity of 0.690476. The ACO based technique have the highest accuracy, Sensitivity and Specificity than the other three (3) technical indicators in predicting the next day closing stock price. Therefore, the optimal prediction of our ACO Agent provides a better forecast than the three initial strategies.

Timetable generation is a very difficult task. It is a time consuming, and arduous process. To manually generate a timetable, takes a lot of time, effort, and manpower. However, a timetable scheduling system is designed for different purposes such as: organizing lectures in higher institutions, private organization, airlines, bus station, etc. This paper tries to minimize the difficulties in generating a timetable for academic purposes, using Logarithmic algorithm, to be precise the modified Quicksort algorithm for its design. The algorithm is designed to eradicate collisions on the timetable, and to run in parallel. This helps to minimize the human errors, improve the accuracy of the timetable scheduling process as well as the computation time. To this extent, a Paperless Master Timetable Scheduling System (PMTSS) was proposed and implemented tin this paper to achieve the said requirements. The system can be installed on any android or windows platform. The content of the design also provides exciting services such as: Live Chat for Administrators, Lecturers and Students, Timetable alertsetc. The paperless timetable scheduling system involves dynamic system utilization and modifications.

Reducing the risk pose by phishers and other cybercriminals in the cyber space requires a robust and automatic means of detecting phishing websites, since the culprits are constantly coming up with new techniques of achieving their goals almost on daily basis. Phishers are constantly evolving the methods they used for luring user to revealing their sensitive information. Many methods have been proposed in past for phishing detection. But the quest for better solution is still on. This research covers the development of phishing website model based on different algorithms with different set of features in order to investigate the most significant features in the dataset.

Attacks on various computer networks are usually in form of patterns of attack. The patterns are recognizable mostly based on the data that the respective packet payloads contain. Attack patterns usually occur as strings or regular expression patterns, which are then converted into their equivalent automata. To create an efficient automata, there is a need for the automata design to consume less memory resources per each state of the automata. This is important whenever the design attempts to detect variations of these patterns. This paper explains the design, structure, and suitability of the hardware memory architecture for a Field Programmable Gate Array (FPGA) based automata design. The new design implementation is based on the input compression technique called Equivalence Classification (EC) which is used to drive a Nondeterministic Fine Automata (NFA) referred to as Equivalence Class Decoding NFA (ECD-NFA). The ECD-NFA approach creates classes of compressed inputs represented by positive integers simply called ECDs, which are the class descriptors. The compressed ECDs are then used to drive the automata, instead of unclassified raw character-inputs. This paper further extends the design by creating a memory grid that utilizes half the total number of required primitive block RAMs (BRAMS). Also, by rewriting the algorithm for the table look-up operation, the design utilizes a minimal number of function generators. Function generators are implemented as 6-input look-up tables (LUTs) on the target Xilinx FPGA Virtex-6 device. The efficiency of such LUT-based designs is determined by the throughput efficiency. The throughput efficiency (TE) is computed based on the ratio of LUTs utilized by the states of the automata and the design throughput. The preliminary results obtained for the TE is 3.55, while the clock rate obtained was 440.51MHz