A system for full-chip and critical net parasitic extraction for ULSI interconnects using a fast 3-D field solver

Bachtold, M.; Spasojevic, M.; Lage, Christian; Ljung, Per

doi:10.1109/43.833201

Cited by 35 publications

(17 citation statements)

References 31 publications

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“…In the area of electromagnetic analysis of complicated geometries of interconnect, most of the recently developed programs have been based on combining discretized integral formulations with accelerated iterative methods [1,2,3,4,5,6,7,8]. Though these programs and techniques have been very effective, there is still no * This work was supported by the Semiconductor Research Corporation, the Marco interconnect focus center, the DARPA neocad program, as well as the grants from the National Science Foundation and Intel Corporation.…”

Section: Introductionmentioning

confidence: 99%

Algorithms in FastImp: a fast and wide-band impedance extraction program for complicated 3-D geometries

Zhu

Song²,

White

2005

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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In this paper we describe the algorithms used in FastImp, a program for accurate analysis of wide-band electromagnetic effects in very complicated geometries of conductors. The program is based on a recently developed surface integral formulation and a precorrected-FFT accelerated iterative method, but includes a new scaling and preconditioning technique as well as a generalized grid interpolation and projection strategy. Computational results are given on a variety of integrated circuit interconnect structures to demonstrate that FastImp is robust and can accurately analyze very complicated geometries of conductors.

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Section: Introductionmentioning

confidence: 99%

Algorithms in FastImp: a fast and wide-band impedance extraction program for complicated 3-D geometries

Zhu

Song²,

White

2005

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Currently, the 3-D interconnect structure is usually generated by 2-D geometries from the layout and design process technology [24]. 2-D geometries include the information of interconnect, such as the shape, layer number, etc.…”

Section: A Hierarchical Partition Of the 3-d Domainmentioning

confidence: 99%

“…They can be classified as two kinds: the local and global ones. The local approaches are well-known flat field solutions that solve the Laplace equation with a preset bias on conductors by using the finite-difference method (FDM) [5], finite-element method (FEM) [2] or boundary-element method (BEM) [6], [21], [24], [25], etc. [15], [17], [18], [23].…”

Section: Introductionmentioning

confidence: 99%

Hierarchical Block Boundary-Element Method (HBBEM): A Fast Field Solver for 3-D Capacitance Extraction

Wang

2004

IEEE Trans. Microwave Theory Techn.

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Abstract-As feature size decrease, fast and accurate parasitic capacitance extraction has become increasingly critical for verification and analysis in very large scale integration design. In this paper, a fast hierarchical-block boundary-element method based on the boundary-element method (BEM) is presented for threedimensional (3-D) capacitance extraction, which can give out the global capacitance matrix directly. It assigns the global computation of 3-D domain into local computation in BEM blocks by hierarchical partition 3-D structure. The boundary capacitance matrix (BCM) is computed in the BEM block using all the known conditions. Reuse technology can decrease the running time. After merging the BCMs of all BEM blocks, the global capacitance matrix for a given set of conductors can be computed. Numerical results show that this global hierarchical approach can get very high speed in 3-D computation with equal accuracy as the 3-D field solver.Index Terms-Boundary-element method (BEM), capacitance extraction, hierarchical, very large scale integration (VLSI).

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“…It is well known that 2D/2.5D capacitance extraction algorithms are fast but inaccurate [1]. For critical nets and clock trees, the industry require 3D algorithms that have high accuracy [3].…”

Section: Introductionmentioning

confidence: 99%

A Divide-and-Conquer Algorithm for 3-D Capacitance Extraction

Shi

2004

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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We present a new algorithm to improve the 3D boundary element method (BEM) for capacitance extraction. We partition large interconnect structures into small sections, set new boundary conditions using the border for each section, solve each section, and then combine the results to derive the capacitance. The target applications are critical nets, clock trees, or packages where 3D accuracy is required.Our algorithm is a significant improvement over the traditional BEMs and their enhancements, such as the "window" method where conductors far away are dropped, and the "shield" method where conductors hidden behind other conductors are dropped. Experimental results show that our algorithm is a magnitude faster than the traditional BEM and the window+shield method, for medium to large structures. The error of the capacitance computed by the new algorithm is within 2% for self capacitance and 7% for coupling capacitance, compared with the results obtained by solving the entire system using BEM. Furthermore, our algorithms gives accurate distributed RC, where none of the previous 3D BEM algorithms and their enhancements can.

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A system for full-chip and critical net parasitic extraction for ULSI interconnects using a fast 3-D field solver

Cited by 35 publications

References 31 publications

Algorithms in FastImp: a fast and wide-band impedance extraction program for complicated 3-D geometries

Algorithms in FastImp: a fast and wide-band impedance extraction program for complicated 3-D geometries

Hierarchical Block Boundary-Element Method (HBBEM): A Fast Field Solver for 3-D Capacitance Extraction

A Divide-and-Conquer Algorithm for 3-D Capacitance Extraction

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