A Systematic Approach to Design Low-Power Video Codec Cores

Denolf, Kristof; Chirila-Rus, A.; Schumacher, P.; Turney, Robert D.; Vissers, Kees; Verkest, D.; Corporaal, Henk

doi:10.1155/2007/64569

Cited by 6 publications

(6 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Finally, the last two lines show the best and the worst case of our work, for 4CIF resolution, chosen for their bandwidth requirements, closest to other presented implementations. Note that for easier comparison, we scaled down the power dissipation figures of the designs made in other technologies, to the 90 nm, 0.9 V technology node used in our implementation (last column), using the following expression suggested in [22]:…”

Section: Resultsmentioning

confidence: 99%

“…The presented MPSoC system, called 3MF MPSoC, is intended to support multiple video coding standards (such as MPEG4, AVC/H.264, SVC) for image resolutions up to HDTV and for rates of up to 30 frames per second. We show that for an AVC/H.264 encoder application, even in the context of a small MPSoC system (13 nodes in all), with a universal NoC topology (connection from any to any other node) and heavy inter-node communication (up to 1 GB/s of traffic), the power dissipation of the NoC is not critical and comparable to the power dissipation of the dedicated communication infrastructures [22] and lower than other NoC implementations presented in the literature [16,17].…”

Section: Introduction and Related Workmentioning

confidence: 99%

“…But most of these hardware solutions are dedicated to one particular encoding/decoding algorithm and target one resolution and frame rate. In our previous work [21], we used the same framework to derive the power dissipation of the MPEG4 SP encoder when implemented using a pure functional application mapping and we compared our results with those of a dedicated low power implementation presented in [22].…”

Section: Introduction and Related Workmentioning

confidence: 99%

See 2 more Smart Citations

Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications

Milojevic

Montperrus²,

Verkest

2008

J Sign Process Syst Sign Image Video Technol

Self Cite

View full text Add to dashboard Cite

In the near future, small electronic hand-held devices will be equipped with digital cameras capable of acquiring high resolution images (HDTV) at realtime rates, resulting in video streams of dozens of megabytes per second. The real-time video decoding and especially encoding of such streams with AVC/ H.264 or SVC standards require a huge amount of computing power that, in the case of a hand-held device, has to be delivered under the constraint of low power dissipation. In this paper we present a MultiProcessor System-on-Chip dedicated for high performance, low-power video coding applications using Network-on-Chip (NoC) as communication infrastructure. Extensive experiments have established the power dissipation models of individual NoC components, i.e. network interfaces, routers and wires. Based on these This research has been carried out in the context of IMEC's multimode multimedia program which is partially sponsored by Samsung and Freescale. The authors would also like to thank models and the NoC topology, we build the power model of the complete NoC. For three different implementation scenarios of the AVC/H.264 simple profile encoder we derive the power dissipation of the NoC for image resolutions up to HDTV at rate of 30 frames per second. The results obtained show that for the same application mapping scenario (worst case), moving from CIF to HDTV resolution will result in a 35% increase of the total power dissipation. Finally, for HDTV resolution, the difference in power dissipation between the worst (21 mW) and the best case application mapping scenario is 26%.

show abstract

Section: Resultsmentioning

confidence: 99%

Section: Introduction and Related Workmentioning

confidence: 99%

Section: Introduction and Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications

Milojevic

Montperrus²,

Verkest

2008

J Sign Process Syst Sign Image Video Technol

Self Cite

View full text Add to dashboard Cite

show abstract

“…The functional block diagram of the MPEG-4 SP encoder implemented in [14] is shown on Fig.2 with computational, on-chip and off-chip memory blocks represented respectively with white, light and dark grey boxes. For each link between two blocks we indicate the number of bytes that have to be accessed for the computation of each new macroblock (MBL).…”

Section: Mpeg-4 Sp Encoder Bandwidth Requirementsmentioning

confidence: 99%

“…Recently the power efficiency of the NoC in the context of a heterogeneous SoC designed for high performance, low-power multimedia applications has been discussed in [8]. On the other hand an important number of dedicated low power MPEG-4 implementations on FPGAs and ASICs have been proposed in the literature recently [9], [10], [11], [12], [13], [14].…”

Section: Introductionmentioning

confidence: 99%

Power dissipation of the network-on-chip in a system-on-chip for MPEG-4 video encoding

Milojevic

Montperrus²,

Verkest

2007

2007 IEEE Asian Solid-State Circuits Conference

Self Cite

View full text Add to dashboard Cite

In this paper we present a Multi-Processor Systemon-Chip (MPSoC) platform with six computational and four memory nodes interconnected with Arteris Network-on-Chip (NoC). The platform is dedicated for real-time video encoding applications for high resolution images (HDTV) and frame rates of up to 30fps. Extensive experiments established the power dissipation models of all individual NoC components, i.e. network interfaces, routers and wires. Based on these power models and the NoC topology we built the power model of the complete NoC. Finally we derive the power dissipation of the NoC for MPEG4 simple profile encoder. The results show that depending on the image resolution the power dissipation of the communication infrastructure vary between 15 and 22mW, which is comparable with the state of the art dedicated low-power implementations.

show abstract

Throughput-Buffering Trade-Off Exploration for Cyclo-Static and Synchronous Dataflow Graphs

Stuijk

Geilen

Basten

2008

IEEE Trans. Comput.

116

161

View full text Add to dashboard Cite

Abstract-Multimedia applications usually have throughput constraints. An implementation must meet these constraints, while it minimizes resource usage and energy consumption. The compute intensive kernels of these applications are often specified as Cyclo-Static or Synchronous Dataflow Graphs. Communication between nodes in these graphs requires storage space which influences throughput. We present an exact technique to chart the Pareto space of throughput and storage trade-offs, which can be used to determine the minimal buffer space needed to execute a graph under a given throughput constraint. The feasibility of the exact technique is demonstrated with experiments on a set of realistic DSP and multimedia applications. To increase scalability of the approach, a fast approximation technique is developed that guarantees both throughput and a, tight, bound on the maximal overestimation of buffer requirements. The approximation technique allows to trade off worst-case overestimation versus run-time.

show abstract

A Systematic Approach to Design Low-Power Video Codec Cores

Cited by 6 publications

References 13 publications

Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications

Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications

Power dissipation of the network-on-chip in a system-on-chip for MPEG-4 video encoding

Throughput-Buffering Trade-Off Exploration for Cyclo-Static and Synchronous Dataflow Graphs

Contact Info

Product

Resources

About