Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications

Milojevic, Dragomir; Montperrus, Luc; Verkest, D.

doi:10.1007/s11265-008-0251-1

Cited by 12 publications

(3 citation statements)

References 22 publications

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“…In this work, we consider a case study based on the 3MF MPSoC platform developed by IMEC and the ULB [24]. This case study has been implemented using MATLAB® and all data were coded using matrices.…”

Section: Implementation and Experimental Resultsmentioning

confidence: 99%

MCDA-based methodology for efficient 3D-design space exploration and decision

Doan

Robert

Smety

et al. 2010

2010 International Symposium on System on Chip

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Recently, the academic and industrial communities have proposed new technologies in order to overcome the physical limitations of the silicon, and among them 3D-Stacked Integrated Circuits (3D-SIC). Manufacturing of 3D-SICs consists in piling up conventional CMOS ICs and creating vertical interconnections between them. This offers new perspectives and levels of performance but the question of efficiently designing them arises since the solution space increases significantly. This paper presents a first approach based on a multi-criteria method in order to be able to efficiently design 3D-SIC. The aim of this work is to quickly explore the design space while considering the numerous criteria involved. This work is a first approach that shows a new design method based on the use of MultiCriteria Decision Aid (MCDA) tools for efficient 3D-SIC design. The problem considered in this first approach is a global 3D-floorplanning. This work has shown that using MCDA tools can provide objective information that would not be available with the current conventional design methods. Those information provides deep analyses which could answer some of the questions a designer may have about the design space of a circuit. We believe that, with these promising results, this MCDA-based method will allow designers to overcome the growing complexity of designing 3D-SICs.

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Section: Implementation and Experimental Resultsmentioning

confidence: 99%

MCDA-based methodology for efficient 3D-design space exploration and decision

Doan

Robert

Smety

et al. 2010

2010 International Symposium on System on Chip

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“…In this section, we will briefly explain the implementation of our design method and show some experimental results based on this first approach. In this work, we consider a case study based on the 3MF MPSoC platform developed at IMEC (Milojevic et al ., ). This case study has been implemented using Python (with NumPy), and all data were coded using matrices.…”

Section: Case Study and Implementationmentioning

confidence: 97%

A MOO‐based Methodology for Designing 3D Stacked Integrated Circuits

Doan¹,

Milojevic²,

Robert³

et al. 2013

Multi Criteria Decision Anal

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In the past decades, the micro-electronic industry has been following the Moore's law to improve the performance of integrated circuits (ICs). However, it will probably be impossible to follow this law in the future due to physical limitations appearing with the miniaturization of the transistors below a certain threshold. In order to overcome this problem, new technologies have emerged, and among them the two-dimensional stacked integrated circuits (3D-SIC) have been proposed to keep the Moore's momentum alive. 3D-SICs can bring numerous advantages in the design of future ICs but at the cost of additional design complexity due to their highly combinatorial nature, and the optimization of several conflicting criteria. In this paper, we present a first study of tools that can help the design of 3D-SICs, using multi-objective optimization (MOO). Our study has targeted one of the main issues in the design of 3D-SICs: the floorplanning. This work shows that the use of MOO can provide relevant and objective analysis of the problem that may not be feasible with the current design methods. MOO can allow a quick design space exploration and an improvement of the current design flows. Also, with its flexibility, MOO can cope with the multiple degrees of freedom of 3D-SICs, which enables more design possibilities. We believe that these promising results will help designers to overcome the main difficulties of designing 3D-SICs.

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“…Practical case study: MPSoC for video encoding applications In order to demonstrate the strengths of the proposed design methodology and the practical feasibility of the tool chain using available state of the art tools, we will push a fairly complex design through the complete flow. The system used is the extension of an existing design, dedicated for low-power, advanced video-coding applications from our previous work (see [14]). Simplified block diagram of the system is shown on Figure 2.…”

Section: Ip Modelsmentioning

confidence: 99%

Automated Pathfinding tool chain for 3D-stacked integrated circuits: Practical case study

Milojevic

Carlson

Croes

et al. 2009

2009 IEEE International Conference on 3D System Integration

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New technologies for manufacturing 3D Stacked ICs offer numerous opportunities for the design of complex and efficient embedded systems. But these technologies also introduce many design options at system/chip design level, hard to grasp during the complete design cycle. Because of the sequential nature of current design practices, designers are often forced to introduce design margins to meet required specifications, resulting in sub-optimal designs. In this paper we introduce new design methodology and practical tool chain, called PathFinding Flow, that can help designers to easily trade-off between different system level design choices, physical design and/or technology options and understand their impact on typical design parameters such as cost, performance and power. Proposed methodology and the tool chain will be demonstrated on a practical case study, involving fairly complex Multi-Processor System-on-Chip using Networkon-Chip for communication medium. With this example we will show how High-Level Synthesis can be used to quickly move from high-level to RTL models, necessary for accurate physical prototyping for both computation and communication. We will also show how the possibility of design iteration, through the mechanism of feedback based on physical information from physical prototyping, can improve design performance. Finally, we will show how we can move in no time from traditional 2D to 3D design and how we can measure benefits of such design choice.

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Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications

Cited by 12 publications

References 22 publications

MCDA-based methodology for efficient 3D-design space exploration and decision

MCDA-based methodology for efficient 3D-design space exploration and decision

A MOO‐based Methodology for Designing 3D Stacked Integrated Circuits

Automated Pathfinding tool chain for 3D-stacked integrated circuits: Practical case study

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