A systematic method for modifying march tests for bit-oriented memories into tests for word-oriented memories

Abstract

Abstract-Most memory test algorithms are optimized for a particular memory technology and a particular set of fault models, under the assumption that the memory is bit-oriented, i.e., read and write operations affect only a single bit in the memory. Traditionally, word-oriented memories have been tested by repeated application of a test for bit-oriented memories, whereby a different data background is used during each application. This results in time inefficiencies and limited fault coverage. A systematic way of converting tests for bit-oriented memories into tests for word-oriented memories is presented, distinguishing between interword and intraword faults. The conversion consists of concatenating to the test for interword faults, a test for intraword faults. This approach results in more efficient tests with complete coverage of the targeted faults. Word-oriented memory tests are very important, because most memories have an external data path which is wider than one bit.

Software-Based Self-Test of Set-Associative Cache Memories

“…It behaves as a read&verify operation but the result of the read is not verified. In all the above defined operations DB represents a data background pattern [34], i.e., a generic sequence of bits written in the data array of the cache. For each DB a complemented pattern DB, obtained from DB by complementing its bits, must also be defined.…”

“…By properly implementing the previously defined cache memory operations it is therefore possible to produce test sequences addressing the same type of faults addressed by traditional march tests, i.e., single cell faults, and coupling faults among cache lines either located in a single set or in different sets. Moreover, by translating march tests developed for word-oriented memories [34], it is possible to detect intra-word faults in a single cache line.…”

March Test Generation Revealed

“…In this paper, we focus on bit-oriented memories only. The extension of the obtained march tests to word-oriented memories can be easily done according to the algorithm proposed in [15]. The behavior of an N-cell 1-bit memory (Definition 1) can be formally represented by an Edge-Labeled Directed Graph (ELDG) G defined as…”