March Test Generation Revealed

Abstract

Memory testing commonly faces two issues: the characterization of detailed and realistic fault models and the definition of time-efficient test algorithms. Among the different types of algorithms proposed for testing Static Random Access Memories, march tests have proven to be faster, simpler, and regularly structured. The majority of the published march tests have been manually generated. Unfortunately, the continuous evolution of the memory technology introduces new classes of faults such as dynamic and linked faults and makes the task of handwriting test algorithms harder and not always leading to optimal results. Although some researchers published handmade march tests able to deal with new fault models, the problem of a comprehensive methodology to automatically generate march tests addressing both classic and new fault models is still an open issue. This paper proposes a new polynomial algorithm to automatically generate march tests. The formal model adopted to represent memory faults allows the definition of a general methodology to deal with static, dynamic, and linked faults. Experimental results show that the new automatically generated march tests reduce the test complexity and, therefore, the test time, compared to the well-known state of the art in memory testing.

Genetic Defect Based March Test Generation for SRAM

“…Electrical simulations have been performed using the commercial HSPICE TM simulator while the GMTG has been implemented in about 3,500 lines of C code executed on a 1.8GHz AMD TURION TM laptop equipped with 1GB of RAM and running the Linux operating system. A preliminary set of experiments allowed us to derive the set of tuning parameters for the GMTG 3 . Figure 2 (a) and Figure 2 (b) propose the architecture of a single memory cell including our target collection of defects.…”

“…Functional Fault Models (FFMs) coupled with e cient test algorithms such as march tests (the reader may refer to [1] to understand the concept of march test) have been so far enough to deal with emerging classes of memory defects [1]. FFMs do not depend on the specific memory technology and allow automation of test sequences generation [3]. Exploring the e↵ect of fabrication defects in future technologies, and identifying new classes of FFMs with their relevant test sequences, is a time consuming task up to now mainly performed by hand.…”

Effective Post-Silicon Validation of System-on-Chips Using Quick Error Detection

“…Furthermore, QED can be applied to automatically generated functional tests [8], [10], [31], [34], [50], [55] to improve the error detection latencies and coverage of such tests. QED can also improve the error detection latencies of tests that rely on multipass checking, where tests are run multiple times to determine the expected results and to detect errors.…”

Software-Based Self-Test of Set-Associative Cache Memories

“…March tests are probably the most used class of memory test algorithms [14], [32], [33]. They detect faults by performing write and read&verify operations on the target memory.…”