Effective Post-Silicon Validation of System-on-Chips Using Quick Error Detection

Abstract

This paper presents the Quick Error Detection (QED) technique for systematically creating families of postsilicon validation tests that quickly detect bugs inside processor cores and uncore components (cache controllers, memory controllers, and on-chip interconnection networks) of multicore system on chips (SoCs). Such quick detection is essential because long error detection latency, the time elapsed between the occurrence of an error due to a bug and its manifestation as an observable failure, severely limits the effectiveness of traditional post-silicon validation approaches. QED can be implemented completely in software, without any hardware modification. Hence, it is readily applicable to existing designs. Results using multiple hardware platforms, including the Intel Core TM i7 SoC, and a state-of-the-art commercial multicore SoC, along with simulation results using an OpenSPARC T2-like multicore SoC with bug scenarios from commercial multicore SoCs demonstrate: 1) error detection latencies of post-silicon validation tests can be very long, up to billions of clock cycles, especially for bugs inside uncore components; 2) QED shortens error detection latencies by up to nine orders of magnitude to only a few hundred cycles for most bug scenarios; and 3) QED enables up to a fourfold increase in bug coverage.

Emphasizing Functional Relevance Over State Restoration in Post-Silicon Signal Tracing

“…Many existing post-silicon debug technique can benefit from PRoN and its improved functionally relevant signals. These include trace analysis-based SoC protocol debug [14], [38], post-silicon validation and trace signal selection via bitflip detection [34], [35], post-silicon bug localization, and validation for processors [24], [28], [29], [36].…”

Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience)

“…We utilize EDDI with store-readback [54] to maximize coverage by ensuring that values are written correctly. From Table XIII, it is clear why store-readback is important for EDDI.…”

Probabilistic bug-masking analysis for post-silicon tests in microprocessor verification

“…Other approaches leverage formal models, often specified through architectural description languages [10]. Researchers have also proposed solutions that create tests with self-checking properties, so to overcome low observability in post-silicon validation without additional instrumentations (e.g., scan chain, design-fordebug network) [7,9,16]. These self-checking approaches use either reversing [16], equivalent [7], or repeated operations [9]; however, they may not reflect realistic program sequences.…”

“…Researchers have also proposed solutions that create tests with self-checking properties, so to overcome low observability in post-silicon validation without additional instrumentations (e.g., scan chain, design-fordebug network) [7,9,16]. These self-checking approaches use either reversing [16], equivalent [7], or repeated operations [9]; however, they may not reflect realistic program sequences. Information-flow analysis has been investigated extensively in the computer security area [3,12,14].…”