A taxonomy of parallel sorting

Abstract

We propose a taxonomy of parallel sorting that encompasses a broad range of array-and file-sorting algorithms. We analyze how research on parallel sorting has evolved, from the earliest sorting networks to shared memory algorithms and VLSI sorters.In the context of sorting networks, we describe two fundamental parallel merging schemes: the odd-even and the bitonic merge. We discuss sorting algorithms that evolved from these merging schemes for parallel computers, whose processors communicate through interconnection networks such as the perfect shuffle, the mesh, and a number of other sparse networks. Following our discussion of network sorting algorithms, we describe how faster algorithms have been derived from parallel enumeration sorting schemes, where, with a shared memory model of parallel computation, keys are first ranked and then rearranged according to their rank.Parallel sorting algorithms are evaluated according to several criteria related to both the time complexity of an algorithm and its feasibility from the viewpoint of computer architecture. We show that, in addition to attractive communication schemes, network sorting algorithms have nonadaptive schedules that make them suitable for implementation. In particular, they are easily generalized to block sorting algorithms, which utilize limited parallelism to solve large sorting problems. We also address the problem of sorting large mass-storage files in parallel, using modified disk devices or intelligent bubble memory. We conclude by mentioning VLSI sorting as an active and promising direction for research on parallel sorting.

Swapping labeled tokens on graphs

“…We generalize this argument to parallel sorting algorithms on an SIMD machine consisting of several processors with local memory which are connected by a network [1] For example, it is known that there is a parallel sorting algorithm with O( √ n) rounds for a √ n × √ n mesh [12]. Thus, we have OPT(f 0 ) = O(n 3/2 ) for token swapping on such meshes.…”

“…Thus, one interesting research topic is minimizing the number of bars in a ladder lottery for a given permutation π. This minimization problem on ladder lottery can be solved by counting the number of "inversions" in π [8,10], where a pair (p i , p j ) in π is called an inversion in π if p i > p j and i < j; for example, there are four inversions in the permutation (4,2,1,3), that is, (4, 2), (4, 1), (4,3) and (2,1), and hence the ladder lottery in Fig. 2(a) has the minimum number of bars.…”

Multiple Instruction Multiple Data (MIMD) Implementation on Clusters of Terminals

“…[14] There are numerous technologies and standards used to construct distributed computations, including some which are specially designed and optimize for that purpose, such as Remote Procedure Calls (RPC), Remote Method Invocation (RMI) or Net Remoting. [5] Organizing the interaction between each computer is of prime importance. In order to be able to use the widest possible range and types of computers, the protocol or communication channel should not contain or use any information that may not be understood by certain machines.…”

“…The types of distributed systems are based on Flynn's taxonomy of systems: -[1] Single instruction single data (SISD) [2] Single instruction multiple data (SIMD) [3] Multiple instruction single data (MISD) [4] Multiple instruction multiple data (MIMD) [5] Single program multiple data (SPMD)…”

Logarithmic time cost optimal parallel sorting is not yet fast in practice

“…This paper gives only a brief description of the implementation, providing a crude base for discussing its time requirement. Figure 2 outlines (5) for each processor in P do begin (6) Read facts from the stack (7) InitiateProcessors (8) for Stage := 1 to 3 l o g n do begin (9) ComputeWhoIsWho (10) CopyNewUpToUp (11) MakeSamples (12) MergeWithHelp end end end When the algorithm starts, one single CREW PRAM processor is running, and the problem instance and its size, n, are stored in the global memory. Statement (1{3) are executed by this single processor.…”